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Volumn 17, Issue 11, 1996, Pages 509-511

Fully depleted dual-gated thin-film SOI P-MOSFET's fabricated in SOI islands with an isolated buried polysilicon backgate

Author keywords

[No Author keywords available]

Indexed keywords

EPITAXIAL GROWTH; INTERFACES (MATERIALS); SEMICONDUCTING FILMS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR GROWTH; SILICON ON INSULATOR TECHNOLOGY;

EID: 0030283640     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.541764     Document Type: Article
Times cited : (41)

References (8)
  • 1
    • 0029321531 scopus 로고
    • Low defect silicon epitaxial lateral overgrowth planar SOI islands adjacent to selective epitaxial growth (SEG)
    • J. Kessler, J. Glenn Jr., and G. W. Neudeck, "Low defect silicon epitaxial lateral overgrowth planar SOI islands adjacent to selective epitaxial growth (SEG)," Microelectron. Eng., vol. 28, no. 1-4, pp. 435-438, 1995.
    • (1995) Microelectron. Eng. , vol.28 , Issue.1-4 , pp. 435-438
    • Kessler, J.1    Glenn Jr., J.2    Neudeck, G.W.3
  • 2
    • 0000990985 scopus 로고
    • A fully planar method for creating adjacent self-isolating silicon on insulator by epitaxial lateral overgrowth
    • J. L. Glenn Jr., G. W. Neudeck, C. K. Subramanian, and J. P. Denton, "A fully planar method for creating adjacent self-isolating silicon on insulator by epitaxial lateral overgrowth," Appl. Phys. Lett., vol. 60, no. 4, pp. 483-485, 1992.
    • (1992) Appl. Phys. Lett. , vol.60 , Issue.4 , pp. 483-485
    • Glenn Jr., J.L.1    Neudeck, G.W.2    Subramanian, C.K.3    Denton, J.P.4
  • 3
    • 0029534237 scopus 로고
    • Fully depleted dual-gated thin-film SOI P-MOSFET with an isolated buried polysilicon backgate
    • Tucson, AZ, Oct. 4-7
    • J. P. Denton and G. W. Neudeck, "Fully depleted dual-gated thin-film SOI P-MOSFET with an isolated buried polysilicon backgate," in IEEE 1995 SOI Conf., Tucson, AZ, Oct. 4-7, 1995, pp. 135-136.
    • (1995) IEEE 1995 SOI Conf. , pp. 135-136
    • Denton, J.P.1    Neudeck, G.W.2
  • 4
    • 0029520010 scopus 로고
    • Back gated CMOS on SOIAS for dynamic threshold voltage control
    • Dec.
    • I. Yang, C. Vieri, A. Chandrakasan, and D. A. Antoniadis, "Back gated CMOS on SOIAS for dynamic threshold voltage control," in IEDM Tech. Dig., Dec. 1995, pp. 977.
    • (1995) IEDM Tech. Dig. , pp. 977
    • Yang, I.1    Vieri, C.2    Chandrakasan, A.3    Antoniadis, D.A.4
  • 6
    • 0027593145 scopus 로고
    • Interface characterization of fully depleted SOI MOSFET's by a threshold-voltage method
    • P. C. Yang and S. S. Li, "Interface characterization of fully depleted SOI MOSFET's by a threshold-voltage method," Solid-State Electron., vol. 36, no. 5 pp. 801, 1993.
    • (1993) Solid-State Electron. , vol.36 , Issue.5 , pp. 801
    • Yang, P.C.1    Li, S.S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.