High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: Ψ) SOI wafer

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1995, Pages 33-34

  Horiuchi, Masatada ^a   Teshima, Tatsuya ^a   Tokumasu, Kazuya ^a   Yamaguchi, Ken ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GRAIN BOUNDARIES; ION IMPLANTATION; LEAKAGE CURRENTS; MASKS; MOS DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; ULSI CIRCUITS;

CONVENTIONAL MOS PROCESS; DRAIN CONDUCTANCE PROPERTIES; ELECTRICALLY DETERIORATED MATERIAL; EPITAXIAL CHANNEL DEVICE PROPERTIES; GATE ELECTRODE MASK; HIGH TEMPERATURE ANNEALING; POLYSILICON INTERLAYERED; THIN OXIDE;

MOSFET DEVICES;

EID: 0029482142     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)