Limitations and challenges of multi-gigabit dram circuits

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1996, Pages 2-7

  Itoh, Kiyoo ^a   Nakagome, Yoshinobu ^a   Kimura, Shin'ichiro ^a   Watanabe, Takao ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT THEORY; DIELECTRIC FILMS; LEAKAGE CURRENTS; MOSFET DEVICES; PERMITTIVITY; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR JUNCTIONS; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES;

BURIED OXIDE FILM; HIGH SPEED COLUMN MODULES; MULTI DATA BIT CHIP CONFIGURATION; POTENTIAL BARRIER; SHORT CHANNEL EFFECTS; SUBSTRATE FLOATING EFFECT;

RANDOM ACCESS STORAGE;

EID: 0029715043     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (24)