Design and performance considerations for sub-0.1 μm double-gate SOI MOSFETs

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1994, Pages 747-750

  Wong, Hon Sum ^a   Frank, David J ^a   Taur, Yuan ^a   Stork, Johannes M C ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; DIFFUSION IN SOLIDS; ELECTRIC CURRENT MEASUREMENT; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY;

GATE DELAYS; SHORT CHANNEL IMMUNITY;

MOSFET DEVICES;

EID: 0028756972     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)