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Volumn , Issue , 1993, Pages 127-130

High Performance 0.1 μm CMOS Devices with 1.5 V Power Supply

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); MOSFET DEVICES; POWER SUPPLY CIRCUITS; SEMICONDUCTOR DEVICE MANUFACTURE; ULSI CIRCUITS;

EID: 0027879328     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (96)

References (10)
  • 1
    • 0016116644 scopus 로고
    • Design of ion-implanted MOSFET's with very small physical dimensions
    • R.H. Dennard et al, "Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions", IEEE J. Solid-State Circuits, vol. SC-9, no. 5, p. 256, 1974.
    • (1974) IEEE J. Solid-State Circuits , vol.SC-9 , Issue.5 , pp. 256
    • Dennard, R.H.1
  • 2
    • 0026852069 scopus 로고
    • A high performance 0.25 μm CMOS technology: I-design and characterization
    • W.H. Chang et al, "A High Performance 0.25 μm CMOS Technology: I-Design and Characterization", IEEE Trans. Electron Devices, voL ED-39, no. 4, p. 959, 1992.
    • (1992) IEEE Trans. Electron Devices , vol.ED-39 , Issue.4 , pp. 959
    • Chang, W.H.1
  • 3
    • 84866212857 scopus 로고
    • High transconductance 0.1 μm PMOSFET
    • Y. Taur et al, "High Transconductance 0.1 μm pMOSFET". in IEDM Tech. Dig., 1992, p. 901.
    • (1992) IEDM Tech. Dig. , pp. 901
    • Taur, Y.1
  • 4
    • 85033822923 scopus 로고    scopus 로고
    • High Performance 0.1 μm nMOSFET's with 10 ps/stage Delay (85 K) at 1.5 V Power Supply
    • Y. Mii et al, "High Performance 0.1 μm nMOSFET's with 10 ps/stage Delay (85 K) at 1.5 V Power Supply", in 1993 Symp. VLSI Technol.Dig..
    • 1993 Symp. VLSI Technol.Dig..
    • Mii, Y.1
  • 6
    • 0025455892 scopus 로고
    • Experimental technology and performance of 0.1-μm-gate-length FET's operated at liquid-nitrogen temperature
    • G.A. Sai-Halasz et al, "Experimental Technology and Performance of 0.1-μm-Gate-Length FET's Operated at Liquid-Nitrogen Temperature", IBM J. Res. Develop., voL 34, no. 4, p. 452, 1990.
    • (1990) IBM J. Res. Develop., voL , vol.34 , Issue.4 , pp. 452
    • Sai-Halasz, G.A.1
  • 7
    • 0025578245 scopus 로고
    • 0.1μm CMOS devices using low-impurity-channel transistors (LICT)
    • M. Aoki et al, "0.1μm CMOS Devices Using Low-Impurity-Channel Transistors (LICT)", in IEDM Tech. Dig., 1990, p. 939.
    • (1990) IEDM Tech. Dig. , pp. 939
    • Aoki, M.1
  • 8
    • 0001750521 scopus 로고
    • Scaling in Si metal-oxide-semiconductor field-effect transistor into the 0.lμm regime using vertical doping engineering
    • R.H. Yan et al, "Scaling in Si Metal-Oxide-Semiconductor Field-Effect Transistor into the 0.lμm Regime Using Vertical Doping Engineering", Appl. Phys. Lett., vol. 59, p. 3315, 1991.
    • (1991) Appl. Phys. Lett. , vol.59 , pp. 3315
    • Yan, R.H.1
  • 9
    • 0027641506 scopus 로고
    • Indium channel implant for improved short-channel behavior of submicrometer NMOSFET's
    • G. Shahidi et al, "Indium Channel Implant for Improved Short-Channel Behavior of Submicrometer NMOSFET's", IEEE Electron Device Lett., vol. 14, no. 8, p. 409, 1993.
    • (1993) IEEE Electron Device Lett , vol.14 , Issue.8 , pp. 409
    • Shahidi, G.1
  • 10
    • 0026869985 scopus 로고
    • A new shift and ratio method for MOSFET channel-length extraction
    • Y. Taur et al, "A New Shift and Ratio Method for MOSFET Channel-Length Extraction", IEEE Electron Device Lett., voL 13, no. 5, p. 267, 1992.
    • (1992) IEEE Electron Device Lett , vol.13 , Issue.5 , pp. 267
    • Taur, Y.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.