A room-temperature silicon single-electron metal-oxide-semiconductor memory with nanoscale floating-gate and ultranarrow channel

Applied Physics Letters

Volumn 70, Issue 7, 1997, Pages 850-852

  Guo, Lingjie ^a   Leobandung, Effendi ^a   Chou, Stephen Y ^a  

^a University of Minnesota ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; DATA STORAGE EQUIPMENT; FABRICATION; GATES (TRANSISTOR); MOSFET DEVICES; OXIDATION; REACTIVE ION ETCHING; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTING SILICON;

COULOMB BLOCKAGE EFFECT; DEBYE SCREENING LENGTH; NANOSCALE FLOATING GATE; SINGLE ELECTRON TRANSISTOR MEMORY; ULTRANARROW CHANNEL;

MOS DEVICES;

EID: 0031077575     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.118236     Document Type: Article

References (8)

1. K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai, and K. Seki, IEEE Trans. Electron Devices 41, 1628 (1994).
2. S. Tiwari, F. Rana, H. Hanai, A. Hartstein, E. F. Crabbe, and K. Chan, Appl. Phys. Lett. 68, 1377 (1996).
3. P. B. Fischer and S. Y. Chou, Appl. Phys. Lett. 62, 2989 (1993).
4. P. B. Fischer and S. Y. Chou, J. Vac. Sci. Technol. B 11, 2524 (1993).
5. E. Leobandung, L. Guo, and S. Y. Chou, J. Vac. Sci. Technol. B 13, 2865 (1995).
6. H. I. Liu, D. K. Biegelsen, F. A. Ponce, N. M. Johnson, and R. F. W. Pease, Appl. Phys. Lett. 64, 1383 (1994).
7. See, for example, J. R. Davis, Instabilities in MOS Devices (Gordon and Breach, New York, 1980).
8. The capacitance between the floating gate and the channel was also taken into account using the image charge method.