Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1998, Pages 407-410

  Wong, Hon Sum Philip ^a   Franks, David J ^a   Solomon, Paul M ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); SILICON ON INSULATOR TECHNOLOGY;

CHANNEL LENGTH GENERATION;

MOSFET DEVICES;

EID: 0032284102     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)