Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 1992-December, Issue , 1992, Pages 553-556

  Frank, D J ^a   Laux, S E ^a   Fischetti, M V ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTELLIGENT SYSTEMS; MONTE CARLO METHODS;

DEVICE DESIGN; DIGITAL LOGIC; DUAL GATES; GATE LENGTH; MOS-FET; N-CHANNEL; RING OSCILLATOR;

MOSFET DEVICES;

EID: 85056911965     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1992.307422     Document Type: Conference Paper

References (6)

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2. R.-H. Yan, A. Ourmazd and K. F. Lee, "Scaling the Si MOSFET: From bulk to SOI to bulk, " IEEE Trans. Elec. Dev., vol. 39, p. 1704, July 1992.
3. D. A. Antoniadis and J. E. Chung, "Physics and technology of ultra short channel MOSFET devices, " 1991 IEDM Tech. Dig., p. 21.
4. J.-Y. Tang and S. E. Laux, "MONTE: A program to simulate the heterojunction devices in two dimensions, " IEEE Trans. Comp.-Aided Design, vol. CAD-5, Oct. 1986.
5. R. H. Dennard, "Technology challenges for ultrasmall silicon MOSFET's, " J. Vac. Sci. Technol., vol. 19, p. 537, Sept. 1981.
6. S. E. Laux, M. V. Fischetti and D. J. Frank, "Monte Carlo analysis of semiconductor devices: The DAMOCLES program, " IBM J. Res. Develop., vol. 34, p. 466, 1990.