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Volumn 14, Issue 12, 1993, Pages 569-571

Quantum-Mechanical Effects on the Threshold Voltage of Ultrathin-SOI nMOSFET’s

Author keywords

[No Author keywords available]

Indexed keywords

MOS DEVICES; QUANTUM THEORY; SEMICONDUCTOR DEVICES;

EID: 0027886706     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.260792     Document Type: Article
Times cited : (240)

References (6)
  • 1
    • 0023421993 scopus 로고
    • Double-gate silicon-on-insulator with volume inversion: a new device with greatly enhanced performance
    • F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, “Double-gate silicon-on-insulator with volume inversion: a new device with greatly enhanced performance,” IEEE Electron Device Lett., vol. EDL-8, pp. 410–412, 1987.
    • (1987) IEEE Electron Device Lett. , vol.EDL-8 , pp. 410-412
    • Balestra, F.1    Cristoloveanu, S.2    Benachir, M.3    Brini, J.4    Elewa, T.5
  • 2
    • 0023541365 scopus 로고
    • High performance SOIMOSFET using ultra-thin SOI film
    • M. Yoshimi, T. Wada, K. Kato, and H. Tango, “High performance SOIMOSFET using ultra-thin SOI film,” IEEE IEDM, Tech. Dig., pp. 640–643, 1987.
    • (1987) IEEE IEDM, Tech. Dig. , pp. 640-643
    • Yoshimi, M.1    Wada, T.2    Kato, K.3    Tango, H.4
  • 3
    • 0006589440 scopus 로고
    • 0.1-μm-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer
    • Y. Omura, S. Nakashima, K. Izumi, and T. Ishii, “0.1-μm-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer,” IEEE Trans. Electron. Devices, vol. 40, pp. 1019–1022, 1993.
    • (1993) IEEE Trans. Electron. Devices , vol.40 , pp. 1019-1022
    • Omura, Y.1    Nakashima, S.2    Izumi, K.3    Ishii, T.4
  • 4
    • 0019080344 scopus 로고
    • Theory of the fully-depleted SOS/MOS transistor
    • E. R. Worley, “Theory of the fully-depleted SOS/MOS transistor,” Solid-State Electronics, vol. 23, pp. 1107–1111, 1980.
    • (1980) Solid-State Electronics , vol.23 , pp. 1107-1111
    • Worley, E.R.1
  • 5
    • 85056911965 scopus 로고
    • Monte Carlo simulation of a 30 nm dual-gate MOSFET
    • D. J. Frank, S. E. Laux, and M. V. Fischetti, “Monte Carlo simulation of a 30 nm dual-gate MOSFET,” IEEE IEDM, Tech. Dig., pp. 553–556, 1992.
    • (1992) IEEE IEDM, Tech. Dig. , pp. 553-556
    • Frank, D.J.1    Laux, S.E.2    Fischetti, M.V.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.