History of some early developments in ion-implantation technology leading to silicon transistor manufacturing

Proceedings of the IEEE

Volumn 86, Issue 1, 1998, Pages 111-137

  Fair, Richard B ^a,b  

^a Duke University   (United States)

^b ELECTROCHEMICAL SOCIETY   (United States)

Author keywords

Bipolar transistors; Ion implantation; MOSFET's; Radiation damage induced junctions; Self aligned gate; Silicon doping; Threshold voltage adjustment

Indexed keywords

ANNEALING; BIPOLAR TRANSISTORS; GATES (TRANSISTOR); IMPURITIES; INTEGRATED CIRCUIT MANUFACTURE; MOSFET DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS;

ION BEAM DOPING; SILICON GATE TECHNOLOGY; SILICON TRANSISTOR;

ION IMPLANTATION;

EID: 0031673833     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.658764     Document Type: Article

References (101)

1. R. B. Fair, "Challenges to manufacturing submicron, ultra-large scale integrated circuits," Proc. IEEE, vol. 78, 1687-1705, Nov. 1990.
2. J. A. Hoerni, "Method of manufacturing semiconductor devices," U.S. Patent 3202589, Mar. 20, 1962.
3. W. G. Pfann, "Semiconductor signal translating device," U.S. Patent 2597 028, 1952.
4. "A year best forgotten," Electr. Bus. Today, pp. 49-54, May 1997.
5. J. H. Freeman, "Canal rays to ion implantation: 1886-1986," Radiat. Eff., vol. 100, pp. 161-248, 1986.
6. N. Bohr, "On the theory of the decrease of velocity of moving electrified particles on passing through matter," Phil. Mag., vol. 25, p. 10, 1913.
7. R. S. Ohl, "Semiconductor translating devices," U.S. Patent 2 750 54, June 12, 1956.
8. K. Lark-Horovitz, S. Bentor, and R. E. Davis, "Photoelectric and thermoelectric device utilizing semiconducting material," U.S. Patent 2 588 254, Mar. 4, 1952.
9. G. C. Sziklai, "Multielement semiconductor devices," U.S. Patent 2 735 948, Feb. 21, 1956.
10. W. Shockley, "Forming semiconductive devices by ionic bombardment," U.S. Patent 2 787 564, Apr. 2, 1957).
11. J. W. Moyer, "Method of making P-N junction semiconductor unit," U.S. Patent 2 842 466, July 8, 1958.
12. J. F. Gibbons, "Ion implantation in semiconductors - Part I: Range distribution theory and experiments," Proc. IEEE, vol. 56, p. 295, 1968.
13. _, "Ion implantation in semiconductors-Part II: Damage production and annealing," Proc. IEEE, vol. 60, p. 1062,. 1972.
14. R. S. Ohl, "Properties of ionic bombarded crystals," Bell Syst. Tech. J., vol. 31, p. 104, 1952.
15. E. F. Kingsbury and R. S. Ohl, "Photoelectric properties of ionically bombarded silicon," Bell Syst. Tech. J., vol. 31, p. 802, 1952.
16. C. G. Thornton and L. D. Hanley, "A new high temperature silicon diode," Proc. IRE, vol. 43, p. 186, 1955.
17. W. D. Cussins, "Effects produced by ionic bombardment," Proc. Phys. Soc., vol. B68, p. 213, 1955.
18. F. M. Rourke, J. C. Sheffield, and F. A. White, '"Crystal doping' by ion bombardment," Rev. Sci. Instrum., vol. 32, pp. 455-456, 1961.
19. T. Alvager and N. J. Hansen, "Doping of crystals by ion bombardment to produce solid state detectors," Rev. Sci. Instrum., vol. 33, p. 567, 1962.
20. W. J. King and S. J. Solomon, "PN junctions by ion implantation," in Proc. Spring Meeting Electrochemical Society, May 1962. abstract no. 58.
21. H. Strack, "Ion bombardment of silicon in a glow discharge," J. Appl. Phys., vol. 34, p. 2405, 1963.
22. L. Amadei and A. Goetzberger, "Molybdenum masking of ion bombardment doping of silicon," Solid-State Electron., vol. 7, p. 487, 1964.
23. R. R. Ferber, "Junction formation in silicon by positive ion bombardment," IEEE Trans. Nucl. Sci., vol. NS-10, p. 15, 1963.
24. J. O. McCaldin, "Method of treating semiconductor bodies by ion bombardment," U.S. Patent 3 293 084, Dec. 20, 1966.
25. J. Cohen, R. P. Ruth, J. F. Hon, and R. L. Steele, presented at the Electrochemical Society Spring Meeting, San Francisco, CA, May 1965.
26. J. O. McCaldin, "Method of treating semiconductor device by ionic bombardment," U.S. Patent 3 328 210, June 27, 1967.
27. E. H. Snow, A. S. Grove, B. E. Deal, and C. T. Sah, "Ion transport phenomena in insulating films," J. Appl. Phys., vol. 36, p. 1664, 1965.
28. J. O. McCaldin, "Ion beams and solid slate physics," Nucl. Instrum. Methods, vol. 38, pp. 153-164, 1965.
29. J. W. Mayer, L. Eriksson, and J. A. Davies, Ion Implantation in Semiconductors. New York: Academic, 1970.
30. J. Lindhard, "Influence of crystal lattice on motion of energetic charged particles," Mat. Fys. Medd. Dan. Vid. Selsk., vol. 34, no. 14, 1965.
31. J. A. Davies, G. C. Ball, F. Brown, and B. Domeij, "Range of energetic Xe125 ions in monocrystalline silicon," Can. J. Phys., vol. 42, p. 1070, 1964.
32. K. E. Manchester, C. B. Sibley, and G. Alton, "Doping of silicon by ion implantation," Nucl. Instrum. Methods, vol. 38, pp. 169-174, 1965.
33. W. J. King, J. T. Burrill, S. Harrison. F. Martin, and C. Kellett, "Experience in fabricating semiconductor devices using ion implantation techniques," Nucl. Instrum. Methods, vol. 38, pp. 178-179, 1965.
34. C. M. Kellett, W. J. King, and F. A. Leith, "High energy ion implantation of materials," Air Force Cambridge Research Laboratories, Rep. AFCRL-66-367, May 1966.
35. J. Lindard, M. Scharff, and H. Schiott, "Range concepts and heavy ion ranges," Mat. Fys. Medd. Dan. Vid. Sclsk., vol. 33, no. 1, 1963.
36. R. Connolly, "Ion implantation techniques to effect changes in semicons," Electron. News, June 28, 1965.
37. E. H. Snow and B. E. Deal, "Polarization phenomena and other properties of phosphosilicate glass films on silicon," J. Electrochem. Soc., vol. 113, p. 263, 1966
38. D. R. Kerr and D. R. Young, "Method of improving electrical characteristics of semiconductor devices and products produced," U.S. Patent 3 303 059, Feb. 7, 1967.
39. F. M. Wanlass, "Low stand-by power complementary field effect circuitry," U.S. Patent 3 356 858, Dec. 5, 1967.
40. C. T. Sah, "Evolution of the MOS transistor - From concept to VLSI," Proc. IEEE, vol. 76, p. 1280, 1988.
41. C. M. Osburn and A. Reisman, "Challenges in advanced semiconductor technology for high performance and supercomputing applications," J. Supercomputing, vol. 1, p. 149, 1989.
42. H. A. Klasens and H. Koelmans, "A tin oxide field-effect transistor," Solid State Electron., vol. 7, p. 701, 1964.
43. H. A. Klasens, "Method of manufacturing semiconductor devices and semiconductor devices manufactured by such methods," U.S. Patent 3 442 647, May 6, 1969.
44. T. S. te Velde, "Method of manufacturing a semiconductor device," U.S. Patent 3 481 030, Dec. 2, 1969.
45. H. G. Dill, "Insulated gate field-effect transistor (IGFET) with semiconductor gate electrode," U.S. Patent 3 544 399, Dec. 1, 1970.
46. R. W. Bower, "Field-effect device with insulated gate," U.S. Patent 3 472 712, Oct. 14, 1969.
47. "Getting the MOSt," Electronics, p. 52, Oct. 13, 1970.
48. R. E. Kerwin, D. L. Klein, and J. C. Sarace, "Method for making MIS structures," U.S. Patent 3 475 234, Oct. 28, 1969.
49. Federal Supplement 374 F. Supp. 1166, 1974.
50. B. G. Watkins, "IGFET comprising N-type silicon substrate, silicon oxide gate insulator and P-type polycrystalline silicon gate electrode," U.S. Patent 3 576 473, Apr. 27, 1971.
51. R. W. Bower and R. G. Dill, "Insulated gate field effect transistors fabricated using the gate as a source-drain mask," in Proc. IEEE Int. Electron Devices Meeting, Washington, D.C., Oct. 26-28, 1966, paper. 16.6.
52. R. W. Bower, H. G. Dill, and K. G. Aubuchon, "Characterization of MOSFET's formed by gate masked ion implantation technique," in Proc. IEEE Int. Electron Devices Meeting, Washington, D.C., Oct. 1967, paper. 6.3.
53. R. W. Bower, "Insulated gate field-effect device having source and drain regions formed in part by ion implantation and method of making same," U.S. Patent 3 615 934, Oct. 26, 1971.
54. R. W. Bower, H. G. Dill, K. G. Aubuchon, and S. A. Thompson, "MOS field effect transistors formed by gate masked ion implantation," IEEE Trans. Electron Devices, vol. ED-15, p. 757, 1968.
55. H. G. Dill, R. W. Bower, and T. N. Toombs, "Ion implanted MOS technology," Radiat. Eff., vol. 7, p. 45, 1971.
56. F. Faggin and T. Klein, "Silicon gate technology," Solid State Electron., vol. 1, p. 1125, 1970.
57. T. E. Seidel and A. U. MacRae, "The isothermal annealing of boron implanted silicon," in Ion Implantation, F. H. Eisen and L. T. Chadderton, Eds. London: Gordon and Breach, 1971, pp. 149-154.
58. K. A. Pickar and J. V. Dalton, "Lifetime effects in ion implanted silicon," in Ion Implantation, F. H. Eisen and L. T. Chadderton, Eds. London: Gordon and Breach, 1971, pp. 125-130.
59. N. G. Blamires, M. D. Matthews, and R. S. Nelson, "Improved profiles of electrical activity in boron implanted Si," Phys. Lett., vol. 28A, p. 178, 1968.
60. D. E. Davies, "Post annealing conductance behavior of implanted layers in silicon," Appl. Phys. Lett., vol. 14, p. 227, 1969.
61. N. G. E. Johansson and J. W. Mayer, "Hall effect measurements on Sb and Ga implanted silicon; anneal behavior and comparison with other species," Solid State Electron., vol. 13, p. 123, 1970.
62. B. L. Crowder and J. M. Fairfield, "High dose implantations of P, As, and Sb in silicon: A comparison of room temperature implantations followed by a 550°C anneal and implantations conducted at 600°C," J. Electrochem. Soc., vol. 117, p. 363, 1971.
63. D. H. Lee and J. W. Mayer, "Ion implanted semiconductor devices," Proc. IEEE, vol. 62, p. 1241, 1974.
64. R. W. Bower, "Device considerations and applications," in Ion Implantation in Semiconductors, J. W. Mayer, L. Eriksson, and J. A. Davies, Eds. New York: Academic, 1970, pp. 224-249.
65. S. Wagner, "Diffusion of boron from shallow ion implants in silicon," J. Electrochem. Soc., vol. 119, p. 1570, 1972.
66. R. Dennard, F. H. Gaensslen, H. Yu, V. L. Rideout, E. Bossons, and A. R. Leblanc, "Design of ion-implanted MOSFET's with very small dimensions," IEEE J. Solid-State Circuits, vol. SC-9, p. 256, 1974.
67. R. B. Fair and J. C. C. Tsai, "The diffusion of ion-implanted As in Si," J. Electrochem. Soc., vol. 122, p. 1689, 1975.
68. W. N. Carr and J. P. Mize, MOS/LSI Design and Application, Texas Instruments Electronic Series. New York: McGraw-Hill, 1972, p. 72.
69. G. Parkinson, "Ion worked circuits for delivery soon," Electron. New, June 28, 1965.
70. A. J. Speth, "Electron beam control of FET characteristics," IBM Tech. Disclosure Bull., vol. 8, p. 638, 1965.
71. C. W. Perkins, K. G. Aubuchon, and H. G. Dill, "Radiation effects in modified oxide insulators in MOS structures," IEEE Trans. Nucl. Sci., vol. NS-15, p. 176, 1968.
72. K. G. Aubuchon, "The use of ion implantation to set the threshold voltage of MOS transistors," in Proc. Int. Conf. Properties and Use of M.I.S. Structures, 1969, pp. 575-590.
73. M. R. MacPherson, "The adjustment of MOS transistor threshold voltage by ion implantation," Appl. Phys. Lett., vol. 18, p. 502, 1971.
74. M. R. MacPherson, "Threshold shift calculations for ion implanted MOS devices," Solid State Electron., vol. 15, p. 1319, 1972.
75. H. G. Dill, R. M. Finnila, A. M. Leupp, and T. N. Toombs, "The impact of ion implantation on silicon device and circuit technology," Solid State Technol., vol. 15, p. 27, Dec. 1972.
76. J. R. A. Beale, "Applications to semiconductor devices," in Proc. Eur. Conf. Ion Implantation, 1970, pp. 81-87.
77. J. MacDougall, K. Manchester, and R. B. Palmer, "Ion implantation offers a bagful of benefits for MOS," Electronics, vol. 43, p. 86, June 22, 1970.
78. R. H. Crawford, "Implanted depletion loads boost MOS array performance," Electronics, vol. 45, p. 85, 1972.
79. J. A. Kerr and L. N. Large, "Semiconductor devices made by ion implantation," in Proc. Int. Conf. Applications of Ion Beams to Semiconductor Technology, 1967, pp. 649-668.
80. V. M. Gusev, Yu. G. Kozlov, and V. G. Naumenko, "High frequency planar silicon transistor based on ion implanted p-n-p structure," Radio Eng. Electron. Phys., vol. 14, p. 1285, 1969.
81. L. E. Miller, "Uniformity of junctions in diffused silicon devices," in Properties of Elemental and Compound Semiconductors, H. Gates, Ed. New York: Interscience, 1960, p. 303.
82. R. B. Fair and J. C. C. Tsai, "A quantitative model of the diffusion of phosphorus in silicon and the emitter dip effect," J. Electrochem. Soc., vol. 124, p. 1107, 1977.
83. L. N. Large and K. G. Hambleton, "The application of ion implantation to semiconductor devices," in Festkorper Problems IX, Advances in Solid State Physics. New York: Pergamon, 1969, pp. 316-337.
84. R. B. Fair and G. R. Weber, " Effect of complex formation on the diffusion of arsenic in silicon," J. Appl. Phys., vol. 44, p. 273, 1973.
85. K. Fujinuma, T. Sakamoto, T. Abe, K. Sato, and Y. Ohmura, "Silicon microwave transistors made by new techniques," presented at the International Electron Devices Meeting, Washington, D.C., 1969.
86. R. B. Fair, R. S. Payne, and G. R. Weber, "Ion implanted base microwave transistors," unpublished.
87. R. B. Fair, "High concentration arsenic diffusion in silicon from A doped oxide source," J. Electrochem. Soc., vol. 119, p. 1389, 1972.
88. M. K. Barnowski and D. D. Loper, "Ion implanted bipolar transistor carrier concentration profiles," Solid State Electron., vol. 16, p. 433, 1973.
89. T. W. Sigmon, "Characteristics of high performance microwave transistors fabricated by ion implantation," in Tech. Dig. Int. Electron Devices Meeting, Washington, D.C., 1973, p. 387.
90. V. G. K. Reddi and A. Y. C. Yu, "Ion implantation for silicon device fabrication," Solid State Technol., vol. 15, Oct. 1972, pp. 35-41.
91. R. S. Payne, R. J. Scavuzzo, K. H. Olson, J. M. Nacci, and R. A. Moline, "Fully ion-implanted bipolar transistors," IEEE Trans. Electron Devices, vol. ED-21, p. 273, 1974.
92. T. H. Ning and D. D. Tang, "Bipolar trends," Proc. IEEE, vol. 74, p. 1669, 1986.
93. C. M. Kellett, W. J. King, and F. W. Martin, "Semiconductor resistor containing interstitial and substitutional ions formed by ion implantation method," U. S. Patent 3 341 754, Sept. 12, 1967.
94. J. D. MacDougall, K. E. Manchester, and P. E. Roughan, "High value implanted resistors for microcircuits," Proc. IEEE, vol. 57, p. 1538, 1969.
95. A. U. MacRae, "Device fabrication by ion implantation," Radiat. Eff., vol. 7, p. 59, 1971.
96. T. E. Seidel and W. C. Gibson, "Buried-guarded layer ion implanted resistors," IEEE Trans. Electron Devices, vol. ED-20, p. 744, 1973.
97. J. Shappir, "Semiconductor device and method of manufacturing the device," U.S. Patent 3 921 283, Nov. 25, 1975.
98. F. Fang, M. Hatzakis, and C. H. Ting, "Electron beam fabrication of ion implanted high-performance FET circuits," J. Vac. Sci. Technol., vol. 10, p. 1082, 1973.
99. T. C. Chan and C. Mai, "Method for making a semiconductor device," U.S. Patent 4 553 314, Nov. 19, 1985.
100. W. D. Ryden, M. V. Hanson, G. F. Derbenwick, A. P. Gnadinger, and J. R. Adams, "Zero drain overlap and self aligned contact method for MOS devices," U.S. Patent 4 486 94, Dec. 11, 1984.
101. S. Ogura, "Method of fabricating an MOS dynamic RAM with lightly doped drain," U.S. Patent 4 366 613, Jan. 4, 1983.