Generalized scale length for two-dimensional effects in MOSFET's

IEEE Electron Device Letters

Volumn 19, Issue 10, 1998, Pages 385-387

  Frank, David J ^a,b   Taur, Yuan ^a,b   Wong, Hon Sum P ^a,b  

^a IEEE   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Gate insulator; High k dielectric; MOSFET; Scale length; Short channel effect

Indexed keywords

BOUNDARY CONDITIONS; ELECTRIC INSULATING MATERIALS; MATHEMATICAL MODELS; PERMITTIVITY; SEMICONDUCTING SILICON;

GATE INSULATORS; POISSON'S EQUATION; SHORT CHANNEL EFFECT;

MOSFET DEVICES;

EID: 0032187666     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.720194     Document Type: Article

References (7)

1. J. R. Brews, W. Fichtner, E. H. Nicollian, and S. M. Sze, "Generalized guide for MOSFET miniaturization," IEEE Electron Device Lett., vol. EDL-1, p. 2, 1980.
2. R.-H. Yan, A. Ourmazd, and K. F. Lee, "Scaling the Si MOSFET: From bulk to SOI to bulk," IEEE Trans. Electron Devices, vol. 39, pp. 1704-1710, 1992.
3. K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, "Scaling theory of double-gate SOI MOSFET's," IEEE Trans. Electron Devices, vol. 40, pp. 2326-2329, 1993.
4. T. N. Nguyen, "Small-geometry MOS transistors: Physics and modeling of surface- and buried-channel MOSFET's," Ph.D. dissertation, Stanford Univ., Stanford, CA, Tech. Rep. G545-2, 1984.
5. Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, to be published.
6. Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. K. Ko, and Y. C. Cheng, "Threshold voltage model for deep-submicrometer MOSFET's," IEEE Trans. Electron Devices, vol. 40, pp. 86-95, Jan. 1993.
7. E. Buturla, J. Johnson, S. Furkay, and P. Cottrell, "A new 3-D device simulation formulation," in NASCODE VI. Dublin, Ireland: Boole, 1989, p. 291.