Discrete random dopant distribution effects in nanometer-scale MOSFETs

Microelectronics Reliability

Volumn 38, Issue 9, 1998, Pages 1447-1456

  Wong, Hon Sum Philip ^a   Taur, Yuan ^a   Frank, David J ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMS; COMPUTER SIMULATION; INTEGRATED CIRCUITS; SEMICONDUCTOR DOPING; THREE DIMENSIONAL; THRESHOLD VOLTAGE;

DISCRETE RANDOM DOPANT DISTRIBUTION EFFECTS; DOPANTS;

MOSFET DEVICES;

EID: 0032157146     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/s0026-2714(98)00053-5     Document Type: Article

References (22)

1. Hoeneisen B, Mead CA. Fundamental limitations in microelectronics - I MOS technology. Solid State Electronics 1972;15:819.
2. Keyes RW. Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics. IEEE J Solid State Circuits 1975;245.
3. Wong H-S, Taur Y. Three-dimensional 'atomistic' simulation of discrete random dopant distribution effects in sub-0.1 um MOSFETs. In: International Electron Device Meeting, 1993. p. 705.
4. Mizuno T, Okamura J, Toriumi A. Experimental study of threshold voltage fluctuations using an 8k MOSFETs array. In: VLSI Symposium, 1993. p. 41.
5. De V, Tang X, Meindl J. Random MOSFET parameter fluctuation limits to gigascale integration (GSI). Symposium on VLSI Technology, 1996;198.
6. Stork J. Technology leverage for ultra-low power information systems. IEEE Proceedings 1995;607-618.
7. Frank DJ, Solomon P, Reynolds S, Shin J. Supply and threshold voltage optimization for low power design. In: Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997. p. 317-22.
8. Nishinohara K, Shigyo N, Wada T. Effects of microscopic fluctuations in dopant distributions on MOSFET threshold voltage. IEEE Trans Electron Devices 1992;39:634.
9. Dennard RH. Technology challenges for ultrasmall silicon MOSFETs. J Vac Sci Technol 1981;19(3):537.
10. Hagiwara T, Yamaguchi K, Asai S. Threshold voltage deviation in very small MOS transistors due to local impurity fluctuations. In Symposium on VLSI Technology, 1982. p. 46.
11. Buturla E, Johnson H, Furkay S, Cottrell P. A new 3-D device simulation formulation. In: NASCODE VI: Sixth International conference on the Numerical Analysis of Semiconductor Devices and Integrated Circuits. Boole Press, 1989:291-96.
12. Keyes R. The effect of randomness in the distribution of impurity atoms on FET thresholds. Appl Phys 1975;8:251-59.
13. Burnett D, Sun S-W. Statistical threshold-voltage variation and its impact on supply-voltage scaling. In: Proceedings of SPIE. 2636, 1995. p. 83.
14. Taur Y, Ning T. Fundamentals of modern VLSI devices. Cambridge: Cambridge University Press (in press).
15. Yan R, Ourmazd A, Lee K. Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans Electron Devices 1992;39:1704.
16. Solomon P. A comparison of semiconductor devices for high speed logic. IEEE Proc 1982;70:489.
17. Wong H-SP, Frank D, Solomon PM, Wann H-J, Welser J. Nanoscale CMOS. IEEE Proc (in press).
18. + -polycrystalline Si-Ge gate electrodes. International Electron Devices Meeting 1993;:727.
19. x gate material for submicrometer CMOS technologies. IEEE Electron Device Lett 1993;12:533.
20. Su L et al. A high performance 0.08 μm CMOS. In: Symposium VLSI Technology, 1996. p. 12.
21. Taur Y, Buchanan D, Chen W, Frank D, Ismail K, Lo S-H, Sai-Halasz G, Viswanathan R, Wann H-JC, Wind S, Wong H-S. CMOS scaling into the nanometer regime. IEEE Proc. 1997;85(4):486.
22. Semiconductor industry association (SIA) 4300 Stevens Creek Boulevard Suite 271 San Jose CA 95129 (http://www.sematech.org/public/roadmap/index.htm) 1998. The national technology roadmap for semiconductors.