A comparative study of advanced MOSFET concepts

IEEE Transactions on Electron Devices

Volumn 43, Issue 10, 1996, Pages 1742-1753

  Wann, Clement I I ^a   Noda, Kenji ^b,e   Tanaka, Tetsu ^c   Yoshida, Makoto ^b,d   Hu, Chenming ^f  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

^d NEC CORPORATION   (Japan)

^e FUJITSU LABORATORIES LTD   (Japan)

^f HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; CARRIER CONCENTRATION; CONSTRAINT THEORY; ELECTRIC CURRENT MEASUREMENT; ELECTRIC NETWORK PARAMETERS; ELECTRON ENERGY LEVELS; LOGIC GATES; MATHEMATICAL MODELS; OPTIMIZATION; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; VOLTAGE CONTROL;

ELECTRON MOBILITY; RELATIVE GATE DELAY; SATURATION CURRENT; SHORT CHANNEL EFFECT; SUBTHRESHOLD SWING; THRESHOLD VOLTAGE;

MOSFET DEVICES;

EID: 0030271147     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.536820     Document Type: Article

References (33)

1. S. Malhi and P. Chatterjee, "1-V microsystems scaling oiuschedule for personal communications," IEEE Circuits and Devices Mag., vol. 10, no. 2, pp. 12-17, Mar. 1994.
2. C. Fiegna, H. Twai, T. Wada, T. Saito, E. Sangiorgi, and B. Ricco, "Scaling the MOS transistor below 0.1 -m: Methodology, device structures, and technology requirements," IEEE Trans. Electron Devices, vol. 41, pp. 941-951, June 1994.
3. [31 K. Noda, T. Uchida, T. Tatsumi, T. Aoyama, K. Nakajima, H. Miyamoto, T. Hashimoto, and I. Sasake, "0.1 /um delta-doped MOSFET using post-energy implanting selective epitaxy," in 1994-VLSI Symp. VLSI Technology Dig. Tech. Papers, pp. 19-20.
4. K. Yamaguchi, Y. Shiraki, Y. Katayama, and Y. Murayma, "A new short-channel MOSFET with an atomic-layer-doping impurity profile (ALD-MOSFET)," JpnJ. Appl. Phys., vol. 22, pp. 267-270, 1983.
5. Y. Taur et al, "High performance 0.1 fim CMOS devices with 1.5 V power supply," Int. Electron Devices Meet. Tech. Dig., 1993, pp. 127-130.
6. R. Yan, A. Ourmazd, and K. Lee, "Scaling the Si MOSFET: From bulk to SOI to bulk," IEEE Trans. Electron Devices, vol. 39, pp. 1704-1710, July 1992.
7. T. Hori, "A 0.1 fim CMOS technology with tilt-implanted punchthiough stopper (TIPS)," Int. Electron Devices Meet. Tech. Dig., 1994, pp. 75-78.
8. F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. Ko, and C. Hu, "A dynamic-threshold MOSFET for ultra-low voltage operation," Int. Electron Devices Meet. Tech. Dig., 1994, pp. 809-812.
9. T. Tanaka, K. Suzuki, H. Horie, and T. Sugii, "Ultrafast operation of Vjf, adjusted p+ n+ double-gate SOI MOSFET's," IEEE Electron Device Lett., vol. 15, no. 10, pp. 386-388, Oct. 1994.
10. K. Sunouchi et al., "A surrounding-gate transistor (SGT) cell for 64/256 Mbit DRAM's," Int. Electron Devices Meet. Tech. Dig.. 1990, pp. 23-26.
11. D. Hisamoto, T. Kaga, Y. Kawamoto. and E. Takeda, "A fully-depleted lean-channel transistor (DELTA)-A novel vertical ultrathin SOI MOS-FET," Int. Electron Devices Meet. Tech. Dig., 1989, pp. 833-836.
12. C. Codella and S. Ogura, "Halo doping effects in submicron Dl-LDD device design." Int. Electron Devices Meet. Tech. Dig., 1985, pp. 230-233.
13. [131 C. Rafferty et al, "Explanation of reverse short-channel effect by defect gradients," Int. Electron Devices Meet. Tech. Dig., 1993, pp. 311-314.
14. M. Shin'ichiro, D. Takakuni, M. Yasuytiki, A. Talcahiro, S. Satoshi, and Y. Junzo, "1-V power supply high-speed digital circuits technology with multithreshold-voltage CMOS," IEEE J. Solid-Stale Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
15. H. Horiguchi, S. Takeshi, and K. Itoh, "Switched-source-iinpedance CMOS circuit for low standby subthreshold current giga-scale LSl's," IEEE J. Solid-State Circuits, vol. 28, no. 11, pp. 1131-1135, Nov.l993.
16. [16J Y. Tsividis, Operation and Modeling of the MOS Transistors. New York: McGraw-Hill, pp. 55-56.
17. M. Shur, T. A. Fjeldly, T. Ytterdal, and K. Lee, "Unified MOSFET model," Solid State Electron., vol. 35, no. 12, pp. 1795-1802, 1992.
18. S. Sze, Physics of Semiconductor Devices, 2nd cd. New York: Wiley, . p. 446.
19. J. Gautier, K. Jenkins, and J. Sun, "Body charge related transient effects in Boating body SOI NMOSFETS," Int. Electron Devices Meet. Tech. Dig., pp. 623-626, 1995.
20. C. Wann, C. Hu, K. Noda, D. Sinitsky, F. Assaderaghi, and J. Bokor, "Channel doping engineering for MOSFET with adaptable threshold voltage using body effect for low voltage and low power application," in 1995 Int. Symp. VLSI Technology, Systems, and Applications, Proc. Tech. Papers, pp. 159-163.
21. BSIM3SO1 Manual, http://rely.eecs.berkeley.edu.
22. D. Burnett, K. Erington, C. Subramanian, and K. Baker, "Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits," in 1994 Symp. VLSI Technology Dig. Tech. Papers, pp. 15-16.
23. H. Wong and Y. Taur, "Three-dimensional atomistic simulation of discrete random dopant distribution effects in sub-0.1 jum MOSFET's," Int. Electron Devices Meeting Tech. Dig., 1993, pp. 705-708.
24. T. Mizuno, J. Okamura, and A. Toriumi, "Experimental study of threshold voltage fluctuation using an 8K MOSFET array," 7993 Symp, VLSI Technology Dig. Tech. Papers, pp. 41-42.
25. H. Iwai, H. S. Momose, and Y. Katsumala, "Si-MOSFET scaling down to deep-sub-O.l-micron range and future of silicon LSI," in VLSITSA Proc. Tech. Papers, 1995, pp. 262-267.
26. Z. Liu, C. Hu, J. Huang, T. Chan, M. Jeng, P. Ko, and Y. Cheng, "Threshold voltage model for deep-submicrometer MOSFET's," IEEE Trans. Electron Devices, vol. 40, pp. 86-94, Jan. 1993.
27. Y. Taur, Y. Mil, R. Logan, and H. Wong, "On 'Effect channel length' in 0.1 jum MOSFET's," IEEE Electron Device Lett., vol. 16. no. 4, pp-136-138, Apr. 1995.
28. J. R. Brews, W. Finchtner, E. H. Nicollian, and S. Sze, "Generalized guide for MOSFET miniaturization," Int. Electron Devices Meet. Tech. Dig., 1979, pp. 10-13.
29. M. Rodder, A. Amerasekera, S. Aur, and I. C. Chen, "A study of design/process dependence of 0.25 /m gate length CMOS for improved performance and reliability," Int. Electron Devices Meet. Tech. Dig., 1994, pp. 71-74.
30. W. Chang et al.. "A high-performance 0.25 fim CMOS technology: I design and characterization," IEEE Trans. Electron Devices, vol. 39, pp. 959-966, Apr. 1992.
31. M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, "Sub-50 nm gate length NMOSFET with 10 nm phosphorus source and drain junctions," Int. Electron Devices Meet. Tech. Dig., pp. 119-122, 1993.
32. L. Su, J. Jacobs, J. Chung, and D. Antoniadis, "Short-channel effects in deep-submicrometer SOI MOSFET's," in Proc. 1993 IEEE Int. SOI Conf., pp. 112-113.
33. N. Kistler and J. Woo, "Symmetric CMOS in fully-depleted silicon-oninsulator using p+ polycrystalline Si-Ge gate electrode," Int. Electron Devices Meet. Tech. Dig., 1993, pp. 727-730.