2.0 V, 0.35 μm partially depleted SOI-CMOS technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1997, Pages 583-586

  Mistry, Kaizad ^a   Grula, Gregory ^a   Sleight, Jeffrey ^a   Bair, Lawrence ^a   Stephany, Ray ^a   Flatley, Robert ^a   Skerry, Paul ^a  

^a HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SCHOTTKY BODY TIE TECHNOLOGY; STATIC RANDOM ACCESS MEMORY (SRAM);

MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; SILICON ON INSULATOR TECHNOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 0041958944     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)