Technology and device scaling considerations for CMOS imagers

IEEE Transactions on Electron Devices

Volumn 43, Issue 12, 1996, Pages 2131-2142

  Wong, Hon Sum ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRONIC PROPERTIES; GATES (TRANSISTOR); IMAGING TECHNIQUES; INTEGRATED CIRCUIT MANUFACTURE; LINEAR INTEGRATED CIRCUITS; MOSFET DEVICES; PHOTODIODES; RELIABILITY;

CMOS IMAGERS; DEVICE SCALING; MOS PHOTOGATE;

IMAGE SENSORS;

EID: 0030378204     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.544384     Document Type: Article

References (74)

1. G. Weckler, "Operation of p-n junction photodetectors in a photon flux integrating mode," IEEE J. Solid State Circuits, vol. SC-2, p. 65, 1967.
2. P. Noble, "Self-scanned silicon image detector arrays," IEEE Trans. Electron Devices, vol. ED-15, p. 202, 1968.
3. S. Chamberlain, "Photosensitivity and scanning of silicon image detector arrays," IEEE J. Solid State Circuits, vol. SC-4, no. 6, p. 333, 1969.
4. M. H. White, "Photodiode sensor arrays," in Solid State Imaging, P. Jespers, F. van de Wiele, and M. White, Eds. Leyden, The Netherlands: Noordhoff, 1975, p. 165.
5. T. Nakamura, K. Matsumoto, R. Hyuga, and A. Yusa, "A new MOS image sensor operating in a nondestructive readout mode," in Int. Electron Device Meet., 1986, p. 353.
6. J. Hynecek, "A new device architecture suitable for high-resolution and high performance image sensors," IEEE Trans. Electron Devices, vol. 35, p. 646, 1988.
7. J. Hynecek, "BCMD - An improved photosite structure for high-density image sensors," IEEE Trans. Electron Devices, vol. 38, p. 1011, 1991.
8. E. R. Fossum, "Active pixel sensors: Are CCD dinosaurs?" Proc. SPIE, vol. 1900, p. 2, 1993.
9. _, "Low power camera-on-a-chip using CMOS active pixel sensor technology," in Symp. Low Power Electronic, 1996, p. 74.
10. _, "CMOS image sensors: Electronic camera on a chip," in Int. Electron Device Meet., 1995, p. 17.
11. B. Ackland and A. Dickinson, "Camera on a chip," in Int. Solid State Circuits Conf., 1996, p. 22.
12. H.-S. Wong and W. Yang, "From photons to bits - Is electronic imaging at a watershed?' in Int. Solid State Circuits Conf., 1996, p. 108.
13. H. Kobayashi, J. L. White, and A. A. Abidi, "An analog CMOS network for Gaussian convolution with embedded image sensing," in Int. Solid State Circuits Conf., 1990, p. 216.
14. S. Mendis, S. E. Kemeny, and E. Fossum, "A 128 × 128 CMOS active pixel image sensor for highly integrated imaging systems," in Int. Electron Device Meet., 1993, p. 583.
15. _, "CMOS active pixel imager sensor," IEEE Trans. Electron Devices, p. 452, 1994.
16. R. Nixon, S. Kemeny, C. Staller, and E. Fossum, "256 × 256 256 CMOS active pixel sensor camera-on-a-chip," in Int. Solid State Circuits Conf., 1996, p. 178.
17. R. Panicacci, S. Kemeny, P. Jones, C. Staller, and E. Fossum, "128 Mb/s multiport CMOS binary active pixel image sensor," in Int. Solid State Circuits Conf., 1996, p. 100.
18. F. Andoh, K. Taketoshi, J. Yamazaki, M. Sugawara, Y. Fujita, and K. Mitani, "A 250,000-pixel image sensor with FET amplification at each pixel for high speed television cameras," in Int. Solid State Circuits Conf., 1990, p. 212.
19. H. Kawashima, F. Andoh, N. Murata, K. Tanaka, M. Yamawaki, and K. Taketoshi, "A 1/4 inch format 250k pixel amplified MOS image sensor using CMOS process," in Int. Electron Device Meet., 1993, p. 575.
20. M. Sugawara, H. Kawashima, F. Andoh, N. Murata, Y. Fujita, and M. Yamawaki, "An amplified MOS imager suited for image processing," in Int. Solid State Circuits Conf, 1994, p. 228.
21. W. Yang, "A wide-dynamic-range low-power photosensor array," in Int. Solid State Circuits Conf, 1994, p. 230.
22. B. Fowler, A. E. Gamal, and D. X. D. Yang, "A CMOS area image sensor with pixel-level A/D conversion," in Int. Solid State Circuits Conf., 1994, p. 226.
23. C. Aw and B. Wooley, "A 128 × 128-pixel standard-CMOS image-sensor with electronic shutter," in Int. Solid State Circuits Conf., 1996, p. 180.
24. D. Renshaw, P. Denyer, G. Wang, and M. Lu, "ASIC image sensors," Proc. IEEE ISCAS, p. 3038, 1990.
25. P. Denyer, D. Renahaw, G. Wang, and M. Lu, "CMOS image sensors for multimedia applications," in Proc. IEEE CICC, 1993, pp. 11.5.1-11.5.4.
26. O. Vellacott, "CMOS in a camera," IEE Review, vol. 40, p. 111, 1994.
27. N. Ricquier and B. Dierickx, "Random addressable CMOS image sensor for industrial applications," Sensors and Actuators A, vol. 44, p. 29, 1994.
28. A. Dickinson, B. Ackland, E.-S. Eid, D. Inglis, and E. Possum, "A 256 × 256 CMOS active-pixel image sensor with motion detection," in Int. Solid State Circuits Conf., 1995, p. 226.
29. _, "Standard CMOS active pixel image sensors for multimedia applications," in 16th Conf. Advanced Research in VLSI, Chapel Hill, NC, Mar. 27-29, 1995, pp. 214-224.
30. P. P. K. Lee, R. C. Gee, R. M. Guidash, T.-H. Lee, and E. R. Fossum, "An active pixel sensor fabricated using CMOS/CCD process technology," 1995 IEEE Workshop on Charge Coupled Device and Advanced Image Sensors, Dana Point, CA, 1995.
31. T. Nomoto, R. Hyuga, S. Nakajima, I. Takayanagi, T. Isokawa, R. Ohta, K. Matsumoto, and T. Nakamura, "A 2/3-inch 2M pixel CMD image sensor with multi scanning function," in Int. Solid State Circuits Conf., 1993, p. 196.
32. I. Takayanagi, T. Isokawa, F. Nakamura, and J. Nakamura, "A multiple output CMD imager for real-time image processing," in Int. Electron Device Meet., 1993, p. 579.
33. H.-S. Wong, R. T. Chang, E. Crabbé, and P. Agnello, "CMOS active pixel image sensors fabricated using a 1.8 V, 0.25 μm CMOS technology," 1996, to be published.
34. IBM J. R&D, Special Issue on IBM CMOS Tech., Jan. 1995.
35. R. Dennard et al., "Design of ion-implanted MOSFETs with very small physical dimensions," IEEE J. Solid State Circuits, vol. SC-9, p. 256, 1974.
36. Y. Taur, Y.-J. Mii, D. J. Frank, H.-S. Wong, D. Buchanan, S. Wind, S. Rishton, G. Sai-Halasz, and E. Nowak, "CMOS scaling into the 21st century: 0.1 μm and beyond," IBM J. R&D, vol. 39, p. 245, 1995.
37. Semiconductor Industry Association (SIA), 4300 Stevens Creek Boulevard, Suite 271, San Jose, CA 95129, The National Technology Roadmap for Semiconductors, 1994.
38. R. D. McGrath, "Problems and questions concerning CMOS imager technology," in 1994 Int. CMOS Camera Workshop, Holmdel, NJ, 1994.
39. F. van der Wiele, "Photodiode quantum efficiency," in Solid State Imaging, P. Jespers, F. van de Wiele, and M. White, Eds. Leyden, The Netherlands: Noordhoff, 1975, p. 47.
40. A. J. P. Theuwissen, Solid-State Imaging with Charge-Coupled Devices. Norwell, MA: Kluwer, 1995, p. 134.
41. J. del Alamo, S. Swirhun, and R. M. Swanson, "Simultaneous measurement of hole lifetime, hole mobility, and bandgap narrowing in heavily doped n-type silicon," in Int. Electron Device Meet., 1985, p. 290.
42. S. Swirhun, Y.-H. Kwark, and R. Swanson, "Measurement of electron lifetime, electron mobility, and band-gap narrowing in heavily doped p-type silicon," in Int. Electron Device Med., 1986, p. 24.
43. B. Burkey, W. Chang, J. Littlehale, T. Lee, T. Tredwell, J. Lavine, and E. Trabka, "The pinned photodiode for an interline-transfer CCD image sensor," Int. Electron Device Meet., 1984, p. 28.
44. E. Palik, Handbook of Optical Constants of Solids. New York: Academic, 1985.
45. B. Davari, W.-H. Chang, K. E. Petrillo, C. Y. Wong, D. Moy, Y. Taur, M. R. Wordeman, J. Y. C. Sun, and C. C.-H. Hsu, "A high-performance 0.25-μm CMOS technology: II - Technology," IEEE Trans. Electron Devices, vol. 39, p. 967, Apr. 1992.
46. L. T. Su, H. Hu, J. B. Jacobs, M. Sherony, A. Wei, and D. A. Antoniadis, "Tradeoffs of current drive versus short-channel effect in deep-submicrometer bulk and SOI MOSFET's," in Int. Electron Device Meet., 1994, p. 649.
47. H.-S. Wong, D. Frank, Y. Taur, and J. Stork, "Design and performance considerations for sub-0.1 μm double-gate SOI MOSFET's," in Int. Electron Device Meet., 1994, p. 747.
48. J.-P. Colinge, "Recent advances in SOI technology," in Int. Electron Device Meet., 1994, p. 817.
49. K. L. Saenger, C. C. Cabral, L. A. Clevenger, and R. A. Roy, "Investigation of titanium suicide formation in Ti + Si reactions using infra-red spectroscopy and x-ray diffraction," J. Appl. Phys., vol. 10, p. 5156, May 1995.
50. M. Lanzoni, L. Selmi, R. Bez, and M. Manfredi, "A test pattern to investigate the effect of capping layers on the hot carrier induced photon spectra of MOSFET's," in Int. Conf. Microelectronic Test Structures, 1994, vol. 7, p. 204.
51. H.-S. Wong, Y. Yao, and E. Schlig, "Time-delay-and-integration charge coupled device - Device design and applications," IBM J. R&D, vol. 36, no. 1, p. 83, 1992.
52. S. L. Kosman, E. G. Stevens, J. C. Cassidy, W. C. Chang, P. Roselle, W. A. Miller, M. Mehra, B. O. Burkey, T. H. Lee, G. A. Hawkins, and R. P. Khosla, "A large area 1.3-megapixel full-frame CCD image sensor with a lateral-overflow drain and a transparent gate electrode," in Int. Electron Device Meet., 1990, p. 287.
53. T. H. Lee, W.-C. Chang, W. A. Miller, G. R. Torok, K. Y. Wong, B. C. Burkey, and R. P. Khosla, "A four million pixel CCD image sensor," Proc. SPIE, vol. 1242, p. 10, 1990.
54. J. T. Bosiers, H. L. Peek, A. C. Kleimann, N. J. Daemen, E. Roks, A. G. van der Sijde, R. M. Jansen, and P. Opmeer, "A S-VHS compatible 1/3 inch 720(H) × 588(V) FT-CCD with low dark current by surface pinning," in Int. Electron Device Meet., 1992, p. 97.
55. R. B. Fair and H. W. Wivell, "Zener and avalanche breaktown in asimplanted lo r-voltage Si n-p junctions," IEEE Trans. Electron Devices, vol. ED-32, no. 5, p. 512, 1976.
56. [561 Y. Matsuya and J. Yamada, "1 V power supply, low-power comsumption A/D conversion technique with swing-suppression noise shaping," IEEE J. Solid State Circuits, vol. 29, no. 12, p. 1524, 1994.
57. 2 Interface - 3, Electrochemical Society Meeting Proceedings, H. Massoud, E. Poindexter, and C. Helms, Eds. Pennington, NJ: The Electrochemical Society, 1996, vol. 96-1, pp. 3-14.
58. M. Hiroshima, T. Yasaka, S. Miyazaki, and M. Hiroso, "Electron tunneling through ultra-thin gate oxide formed on hydrogen-terminated Si(100) surfaces," in Int. Conf. Solid State Device and Materials, 1993, p. 624.
59. E. Fossum and R. Barker, "Measurement of hole leakage and impact ionization currents in bistable metal-tunnel oxide-semiconductor junctions," IEEE Trans. Electron Devices, vol. ED-31, no. 9, p. 1168, 1984.
60. H. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, and H. Iwai, "Tunneling gate oxide approach to ultra-high current drive in small-geometry MOSFET's," in Int. Electron Device Meet., 1994, p. 593.
61. W.-H. Chang, B. Davari, M. R. Wordeman, Y. Taur, C. C.-H. Hsu, and M. D. Rodriguez, "A high-performance 0.25-μm CMOS technology: I - Design and characterization." IEEE Trans. Electron Devices, vol. 39, p. 959. Apr. 1992.
62. H.-S. Wong, "Experimental verification of the mechanism of hot-carrier-induced photon emission in n-MOSFET's with a CCD gate structure," in Int. Electron Device Meet., 1991, p. 549.
63. K. Sakui, S. S. Wong, and B. A. Wooley, "The effects of impact ionization on the operation of neighboring devices and circuits," IEEE Trans. Electron Devices, p. 1603, 1994.
64. J. Matsunaga, H. Momose, H. Iizuka, and S. Kohyama, "Characterization of two step impact ionization and its influence in NMOS and PMOS VLSI's," in Int. Electron Device Meet., 1980, p. 736.
65. T. Furuyama, K. Ohuchi, and S. Kohyama, "An electrical mechanism far holding time degradation in dynamic MOS RAM's," IEEE Trans. Electron Devices, vol. ED-26, no. 11, p. 1684, 1979.
66. Foresight User's Manual, Orbit Semiconductor Inc., 1215 Bordeaux Drive, Sunnyvale, CA 94089, July 1992.
67. C. Sodini, S. Wong, and P. Ko, "A framework to evaluate technology and device design enhancements for MOS integrated circuits," IEEE J. Solid State Circuits, vol. 24, no. 1, p. 118, 1989.
68. 3. Huang, Z. Liu, M. Jeng, P. Ko, and C. Hu, "A physical model for MOSFET output resistance," in Int. Electron Device Meet., 1992, p. 569.
69. A. Matsuzawa, "Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment," IEEE J. Solid State Circuits, vol. 29, no. 4, p. 470, 1994.
70. M. White, D. Lampe, F. Blaha, and I. Mack, "Characterization of surface channel CCD image arrays at low light levels," IEEE J. Solid State Circuits, vol. SC-9, p. 1, 1974.
71. K. Sato, K. Fujita, H. Miyazawa, M. Shirai, M. Kobayashi, M. Ishihara, and T. Nakso, "A system-integrated ULSI chip containing eleven 4 Mb RAM's, six 64 kb SRAJVl's and an 18k gate array," in Int. Solid State Circuits Conf., 1992, p. 52.
72. T. Sunaga, H. Miyatake, K. Kitamura, K. Kasuya, T. Saitoh, M. Tanaka, N. Tanigaki, Y. Mori, and N. Yamasaki, "DRAM macros for ASTC chips," IEEE J. Solid State Circuits, vol. 30, no. 9, p. 1006, 1995.
73. Workshop on DRAM-Based Merged DRAM/SRAM/Logic Technology and Application, San Francisco, CA, Feb. 14, 1995.
74. P. Ko, "Approaches to scaling," in VLSI electronics: Micro Structure Science - Advances to MOS Device Physics, N. Einspruch and G. Gilden-blat, Eds. New York: Academic, 1989, vol. 18, pp. 1-37.