High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHz fT

IEEE Electron Device Letters

Volumn 18, Issue 12, 1997, Pages 625-627

  Wann, Clement ^a   Assaderaghi, Fariborz ^a   Shi, Leathen ^a   Chan, Kevin ^a   Cohen, Steve ^a   Hovel, Harry ^a   Jenkins, Keith ^a   Lee, Young ^a   Sadana, Devendra ^a   Viswanathan, Raman ^a   Wind, Shalom ^a   Taur, Yuan ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CURRENT VOLTAGE CHARACTERISTICS; DELAY CIRCUITS; ELECTRIC CURRENTS; ELECTRIC INVERTERS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); MATHEMATICAL MODELS; MOSFET DEVICES; OSCILLATORS (ELECTRONIC); SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES;

FLOATING BODY EFFECT; INVERTER RING OSCILLATOR DELAYS; SHORT CHANNEL CHARACTERISTICS; THERMAL BUDGET OPTIMIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 0031353832     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.644091     Document Type: Article

References (7)

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2. K. Lee et al., "Room temperature 0.1-μm CMOS technology with 11.8ps gate delay," in IEDM Tech. Dig., 1993, pp. 131-134.
3. T. Yoshitomi et al., "High-performance 0.1-μm single gate Co salicide CMOS," in VLSI Symp. Dig. Tech. Papers, 1996, pp. 34-35.
4. 2 dual gate process," in VLSI Symp. Dig. Tech. Papers, 1995, pp. 9-10.
5. Y. Mii, et al., "An ultra-low power 0.1-μm CMOS," in 1994 Symp. VLSI Technol. Dig. Tech. Papers, Honolulu, HI, June 7-9, 1994, pp. 9-10.
6. C. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, "A comparative study of advanced MOSFET structures," IEEE Trans. Electron Devices, vol. 43, pp. 1742-1753, Oct. 1996.
7. L. Su, S. Subbana, E. Crabbe, P. Agnello, E. Nowak, et al., "A high-performance 0.08-μm CMOS," in VLSI Symp. Dig. Tech. Papers, 1996, pp. 12-13.