SYMMETRIC CMOS IN FULLY-DEPLETED SILICON-ON-INSULATOR USING P+-POLYCRYSTALLINESI-GE GATE ELECTRODES

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 727-730

  Kistler, Neal ^a   Woo, Jason ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRODES; SI-GE ALLOYS; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; DOPING (ADDITIVES); GATES (TRANSISTOR); MOSFET DEVICES; SILICON COMPOUNDS;

CHANNEL BEHAVIOR; CHANNEL DOPINGS; FULLY DEPLETED SILICON-ON-INSULATOR; GATE ELECTRODES; POLYCRYSTALLINE; POLYCRYSTALLINE-SI; RING OSCILLATOR; SHORT CHANNELS; SUBTHRESHOLD SLOPE; SYMMETRICS;

REFRACTORY METAL COMPOUNDS; CMOS INTEGRATED CIRCUITS;

CHANNEL DOPING; FULLY DEPLETED SILICON ON INSULATOR (FDSOI); THRESHOLD VOLTAGE;

EID: 0027839378     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. x gate material for sub-micrometer CMOS technologies,” ZEEE Elect. Deu. Lett., EDL-12, p. 533, 1991.
2. J.-M. Hwang and G. Pollack, “New gate electrodes for fully-depleted SOI/CMOS; TiN and poly Si-Ge,” 1992 Int. SOZ Conf. Proc., p. 148.
3. x films,” Proc. 3rd Znt. Symp. on Process Physics and Modeling in Semiconductor Tech., Vol. 93-6,p. 350.
4. D. Hisamoto, et al., “Ultra-thin SOO CMOS with selective CVD tungsten for low resistance source and drain,” in IEDM Tech. Dig., 1992, p. 829.