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Volumn 18, Issue 2, 1997, Pages 74-76

Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY CONDITIONS; COMPUTER SIMULATION; GATES (TRANSISTOR); MATHEMATICAL MODELS; PERMITTIVITY; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SILICA;

EID: 0031079417     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.553049     Document Type: Article
Times cited : (541)

References (13)
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    • H. Pein and J. D. Plummer, "A 3-D sidewall flash EPROM cell and memory array," IEEE Electron Device Lett., vol. 14, pp. 415-417, Aug. 1993.
    • (1993) IEEE Electron Device Lett. , vol.14 , pp. 415-417
    • Pein, H.1    Plummer, J.D.2
  • 6
    • 85056911965 scopus 로고
    • Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?
    • D. Frank, S. Laux, and M. Fischetti, "Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?," in IEDM Tech. Dig., 1992. pp. 553-556.
    • (1992) IEDM Tech. Dig. , pp. 553-556
    • Frank, D.1    Laux, S.2    Fischetti, M.3
  • 7
    • 0028448562 scopus 로고
    • Scaling the MOS transistor below 0.1 μm: Methodology, device structures, and technology requirements
    • C. Fiegna, H. Iwai, T. Wada, M. Saito, E. Sangiorgi, and B. Ricco, "Scaling the MOS transistor below 0.1 μm: Methodology, device structures, and technology requirements," IEEE Trans. Electron Devices, vol. 41, pp. 941-951, 1994.
    • (1994) IEEE Trans. Electron Devices , vol.41 , pp. 941-951
    • Fiegna, C.1    Iwai, H.2    Wada, T.3    Saito, M.4    Sangiorgi, E.5    Ricco, B.6
  • 8
    • 0026169335 scopus 로고
    • Impact of the vertical SOI "DELTA" structure on planar device technology
    • June
    • D. Hisamoto, T. Kaga, and E. Takeda, "Impact of the vertical SOI "DELTA" structure on planar device technology," IEEE Trans. Electron Devices, vol. 38, pp. 1419-1424, June 1991.
    • (1991) IEEE Trans. Electron Devices , vol.38 , pp. 1419-1424
    • Hisamoto, D.1    Kaga, T.2    Takeda, E.3
  • 10
    • 0024626928 scopus 로고
    • Analysis of conduction in fully depleted SOI MOSFET's
    • K. K. Young, "Analysis of conduction in fully depleted SOI MOSFET's." IEEE Trans. Electron Devices, vol. 36, pp. 504-506, 1989.
    • (1989) IEEE Trans. Electron Devices , vol.36 , pp. 504-506
    • Young, K.K.1
  • 11
    • 0026896303 scopus 로고
    • Scaling the Si MOSFET: From bulk to SOI to bulk
    • July
    • R. H. Yan, A. Ourmazd, and K. F. Lee, "Scaling the Si MOSFET: From bulk to SOI to bulk," IEEE Trans. Electron Devices, vol. 39, pp. 1704-1710, July 1992.
    • (1992) IEEE Trans. Electron Devices , vol.39 , pp. 1704-1710
    • Yan, R.H.1    Ourmazd, A.2    Lee, K.F.3
  • 13
    • 0028545015 scopus 로고
    • Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's
    • Nov.
    • Y. Tosaka, K. Suzuki, and T. Sugii, "Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's," IEEE Electron Device Lett., vol. 15, pp. 466-468, Nov. 1994.
    • (1994) IEEE Electron Device Lett. , vol.15 , pp. 466-468
    • Tosaka, Y.1    Suzuki, K.2    Sugii, T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.