Technology challenges for integration near and below 0.1 μm

Proceedings of the IEEE

Volumn 85, Issue 4, 1997, Pages 505-520

  Asai, Shojiro ^a   Wada, Yasuo ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; MOSFET DEVICES; NANOTECHNOLOGY; RANDOM ACCESS STORAGE; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; VOLTAGE CONTROL; WSI CIRCUITS;

BACK GATE INPUT METAL OXIDE SEMICONDUCTOR (BMOS); DOPING FLUCTUATIONS; DYNAMIC RANDOM ACCESS MEMORY (DRAM);

CMOS INTEGRATED CIRCUITS;

EID: 0031121270     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.573738     Document Type: Article

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