Design methodology for minimizing hysteretic VT-variation in partially-depleted SOI CMOS

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1997, Pages 411-414

  Wei, Andy ^a   Antoniadis, Dimitri A ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

THRESHOLD VOLTAGE VARIATION;

ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; SEMICONDUCTOR DIODES; SILICON ON INSULATOR TECHNOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 84886448119     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (0)