CMOS scaling into the nanometer regime

Proceedings of the IEEE

Volumn 85, Issue 4, 1997, Pages 486-503

  Taur, Yuan ^a   Buchanan, Douglas A ^a   Chen, Wei ^a   Frank, David J ^a   Ismail, Khalid E ^a   Shih Hsien, L O ^a   Sai Halasz, George A ^a   Viswanathan, Raman G ^a   Wann, Hsing Jen C ^a   Wind, Shalom J ^a   Wong, Hon Sum ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; ELECTRIC FIELD EFFECTS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES; MOSFET DEVICES; NANOTECHNOLOGY; POWER SUPPLY CIRCUITS; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD ELEMENTS; VLSI CIRCUITS;

DOPANT NUMBER FLUCTUATIONS; SHORT CHANNEL EFFECT;

CMOS INTEGRATED CIRCUITS;

EID: 0031122158     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.573737     Document Type: Article

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