Circuit techniques for low power CMOS GSI

IEEE Symposium on Low Power Electronics

Volumn , Issue , 1996, Pages 193-196

  Bhavnagarwala, Azeez J ^a   De, Vivek K ^a   Austin, Blanca ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL PATH ANALYSIS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRON TRANSPORT PROPERTIES; ENERGY DISSIPATION; INTEGRATED CIRCUIT MANUFACTURE; MOSFET DEVICES; NUMERICAL METHODS; OPTIMIZATION; SEMICONDUCTOR DEVICE MODELS;

CARRIER MOBILITY; CMOS DATAPATH; THRESHOLD VOLTAGE; TOTAL POWER DISSIPATION;

CMOS INTEGRATED CIRCUITS;

EID: 0030412691     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)