Spin-transistor electronics: An overview and outlook

Proceedings of the IEEE

Volumn 98, Issue 12, 2010, Pages 2124-2154

  Sugahara, Satoshi ^a,b   Nitta, Junsaku ^c  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

^c TOHOKU UNIVERSITY   (Japan)

Author keywords

CMOS integrated circuits; half metallic feromagnet; magnetoresistance; nonvolatile logic; power gating architecture; programmable logic; spin transistor; spin transport; spintronics

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEGREES OF FREEDOM (MECHANICS); ELECTRIC NETWORK ANALYSIS; MAGNETORESISTANCE; NANOELECTRONICS; NONVOLATILE STORAGE; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE; SPINTRONICS;

HALF-METALLIC; NON-VOLATILE LOGIC; POWER GATINGS; PROGRAMMABLE LOGIC; SPIN TRANSISTOR; SPIN TRANSPORT;

TRANSISTORS;

EID: 78649354961     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2010.2064272     Document Type: Conference Paper

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