Characteristics and modeling of sub-10-nm planar bulk CMOS devices fabricated by lateral source/drain junction control

IEEE Transactions on Electron Devices

Volumn 53, Issue 9, 2006, Pages 1961-1968

  Wakabayashi, Hitoshi ^a,b   Ezaki, Tatsuya ^b,c   Sakamoto, Toshitsugu ^b   Kawaura, Hisao ^b   Ikarashi, Nobuyuki ^b   Ikezawa, Nobuyuki ^d   Narihiro, Mitsuru ^b   Ochiai, Yukinori ^b,e   Ikezawa, Takeo ^b   Takeuchi, Kiyoshi ^b   Yamamoto, Toyoji ^b   Hane, Masami ^a,b   Mogami, Tohru ^a,b  

^a IEEE   (Japan)

^b NEC CORPORATION   (Japan)

^c HIROSHIMA UNIVERSITY   (Japan)

^d RENESAS TECHNOLOGY CORP   (Japan)

^e JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

CMOS; Drain induced tunneling modulation (DITM); Notched gate electrode; Reverse order source drain (R S D) formation; Source drain (S D) direct tunneling (DT) currents; Sub 10 nm gate length

Indexed keywords

DRAIN INDUCED TUNNELING MODULATION (DITM); GATE LENGTH; NOTCHED GATE ELECTRODES; REVERSE ORDER SOURCE/DRAIN (R-S/D) FORMATION; SOURCE/DRAIN (S/D) DIRECT TUNNELING (DT) CURRENTS;

DRAIN CURRENT; ELECTRIC POTENTIAL; MOSFET DEVICES; QUANTUM THEORY; SEMICONDUCTOR JUNCTIONS;

CMOS INTEGRATED CIRCUITS;

EID: 33846284604     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.880169     Document Type: Article

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