Beyond the conventional transistor

IBM Journal of Research and Development

Volumn 46, Issue 2-3, 2002, Pages 133-168

  Wong, H S Philip ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CARBON NANOTUBES; FIELD EFFECT TRANSISTORS; MICROELECTRONICS; NANOTECHNOLOGY; PERMITTIVITY; SEMICONDUCTOR DEVICE STRUCTURES;

MOORE'S LAW;

CMOS INTEGRATED CIRCUITS;

EID: 0036508039     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.462.0133     Document Type: Review

References (155)

1. Progress in digital integrated electronics
2. Design of ion-implanted MOSFET's with very small physical dimensions
3. Pushing the limits
4. Fundamental limitations in microelectronics - I MOS technology
5. Low power microelectronics - Retrospect and prospect
6. Technology challenges for integration near and below 0.1 μm
7. CMOS scaling into the nanometer regime
8. Nanoscale CMOS
9. Device scaling limits of Si MOSFETs and their application dependencies
10. Fundamental limits of silicon technology
11. Material and process limits in silicon VLSI technology
12. 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays
13. 30 nm and 20 nm physical gate length CMOS transistors
14. 15 nm gate length planar CMOS transistor
15. Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFETs
16. Scaling the gate dielectric: Materials, integration, and reliability
17. Growth and characterization of ultrathin nitrided silicon dioxide films
18. Thermodynamic stability of binary oxides in contact with silicon
19. Ultra high-k metal oxides on Silicon: Processing, characterization, and integration issues
20. Ultrathin high-k gate stacks for advanced CMOS devices
21. Analysis of the design space available for high-k gate dielectric in nanoscale MOSFETs
22. Emission probability of hot electrons from silicon into silicon dioxide
23. Band offsets of wide-band-gap oxides and implications for future electronic devices
24. 3 gate dielectric for ULSI applications
25. Effective electron mobility in Si inversion layers in MOS systems with a high-k insulator: The role of remote phonon scattering
26. Long range coulomb interactions in small Si devices. Part II: Effective electron mobility in thin oxide structures
27. x gate material for submicrometer CMOS technologies
28. Gate dielectrics for sub-100 nm CMOS
29. y gate electrodes for dual gate Si-CMOS devices
30. Novel damage-free direct metal gate process using atomic layer deposition
31. Theory of semiconductor heterojunctions: The role of quantum dipoles
32. Effects of high-k dielectrics on the workfunctions of metal and silicon gates
33. Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process
34. Metal gate workfunction adjustment for future CMOS technology
35. Dual workfunction metal gate CMOS technology using metal interdiffusion
36. Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate
37. Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
38. Silicon-on-insulator gate-all-around device
39. A new scaling methodology for the 0.1-0.025 μm MOSFET
40. Monte Carlo simulation of a 30nm dual-gate MOSFET: How far can Si go?
41. Scaling the Si MOSFET: From bulk to SOI to bulk
42. Scaling theory for double-gate SOI MOSFET's
43. + double-gate SOI MOSFETs
44. Design and performance considerations for Sub-0.1μm double-gate SOI MOSFET's
45. 25 nm CMOS design considerations
46. Novel device options for sub-100 nm CMOS
47. Back-gated CMOS on SOIAS for dynamic threshold voltage control
48. Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation
49. Generalized scale length for two-dimensional effects in MOSFET's
50. Gate length scaling and threshold voltage control of double-gate MOSFETs
51. FinFET - A quasi-planar double-gate MOSFET
52. Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs
53. DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS
54. Analysis of p+ poly Si double-gate thin-film SOI MOSFETs
55. SOI MOSFET effective channel mobility
56. On the universality of inversion-layer mobility in n- and p-channel MOSFET's
57. Experimental evaluation of carrier transport and device design for planar symmetric/asymmetric double-gate/ground-plane cmosfets
58. Electron mobility behavior in extremely thin SOI MOSFETs
59. Performance and reliability concerns of ultra-thin SOI and ultra-thin gate oxide MOSFETs
60. Investigation of SOI MOSFETs with ultimate thickness
61. Electronic structures and phonon-limited electron mobility of double-gate silicon-on-insulator Si inversion layers
62. Monte Carlo simulation of electron transport properties in extremely thin SOI MOSFETs
63. Electron mobility in extremely thin single-gate silicon-on-insulator inversion layers
64. Low field mobility of ultra-thin SOI n- and p-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs
65. Low field electron mobility in double-gate ultra-thin SOI MOSFETs
66. Wire channel and wrap around gate metal oxide semiconductor field effect transistors with a significant reduction of short channel effects
67. Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel
68. Novel silicon epitaxy for advanced MOSFET devices
69. Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy
70. Triple-self-aligned, planar double-gate MOSFETs: Devices and circuits
71. Thin-film silicon-on-insulator (SOI) device applications of selective epitaxial growth
72. A novel high-speed silicon bipolar transistor utilizing SEG and CLSEG
73. Extremely thin and defect-free si-on-insulator fabrication by tunnel epitaxy
74. 50-nm-thick siliconon-insulator fabrication by advanced epitaxial lateral overgrowth: Tunnel epitaxy
75. Ultra-thin, Highly uniform thin film SOI MOSFET with low series resistance fabricated using pattern-constrained epitaxy (PACE)
76. Sub 50-nm FinFET: PMOS
77. A fully depleted lean-channel transistor (DELTA) - A novel vertical ultra thin SOI MOSFET
78. A sub-40 nm body thickness N-type FinFET
79. Sub-60-nm quasi-planar FinFETs fabricated using a simplified process
80. t asymmetric-gate FinFET devices
81. FinFET process technology for nanoscale CMOS
82. A folded-channel MOSFET for deep-sub-tenth micron era
83. Modeling line edge roughness effects in sub 100 nanometer gate length devices
84. Monte Carlo simulation of transport in technologically significant semiconductors of the diamond and zinc-blende structures - Part II: Submicrometer MOSFETs
85. Accurate characterization of electron and hole inversion-layer capacitance and its impact on low voltage operation of scaled MOSFETs
86. The ballistic FET: Design, capacitance and speed limit
87. On the mobility versus drain current relation for a nanoscale MOSFET
88. x substrates
89. High-mobility p-channel metal-oxidesemiconductor field-effect transistors on strained Si
90. Strain dependence of the performance enhancement in strained-Si n-MOSFETs
91. Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys
92. Hole mobility improvement in silicon-on-insulator and bulk silicon transistors using local strain
93. Transconductance enhancement in deep submicron strained-Si n-MOSFETs
94. Advanced SOI-MOSFETs with strained-Si channel for high speed CMOS - Electron/hole mobility enhancement
95. Si/SiGe CMOS: Can it extend the lifetime of Si
96. Strain relaxation and dislocations in SiGe/ Si structures
97. 1-x structures for III/V integration with Si and high mobility two-dimensional electron gases in Si
98. Electron transport properties of Si/SiGe heterostructures: Measurements and device implications
99. Strained Si NMOSFETs for high performance CMOS technology
100. SiGe-on-insulator prepared by wafer bonding and layer transfer for high-performance field-effect transistors
101. Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding
102. Electron mobility enhancement in strained-Si n-MOSFETs fabricated on SiGe-on-insulator (SGOI) substrates
103. Advanced SOI p-MOSFETs with strained-Si channel on SiGe-on-insulator substrate fabricated by SIMOX technology
104. Fabrication of strained Si on an ultrathin SiGe-on-insulator substrate with a high-Ge fraction
105. Novel fabrication technique for relaxed SiGe-on-insulator substrates without thick SiGe buffer structures
106. New approach to the growth of low dislocation relaxed SiGe material
107. Helical microtubules of graphitic carbon
108. Single-shell carbon nanotubes of 1-nm diameter
109. Carbon nanotubes: Nanomechanics, manipulation, and electronic devices
110. Room-temperature transistor based on a single carbon nanotube
111. Single- and multi-wall carbon nanotube field-effect transistors
112. Synthesis of large arrays of well aligned carbon nanotubes on glass
113. A nanotube based field-emission flat panel display
114. Carbon nanotube membranes for electrochemical energy storage and production
115. Nanotubes as nanoprobes in scanning probe microscopy
116. Covalently functionalized nanotubes as nanometre-sized probes in chemistry and biology
117. Exploiting the properties of carbon nanotubes for nanolithography
118. Disorder, pseudospins, and backscattering in carbon nanotubes
119. Electronic structure of atomically resolved carbon nanotubes
120. Carbon nanotube inter- and intramolecular logic gates
121. Ambipolar electrical transport in semiconducting single-wall carbon nanotubes
122. Logic circuits with carbon nanotube transistors
123. Heterostructures of single-walled carbon nanotubes and carbide nanorods
124. Carbon nanotube field effect transistors for logic applications
125. Optimized contact configuration for the study of transport phenomena in ropes of single-wall carbon nanotubes
126. Carbon nanotubes as long ballistic conductors
127. Scanned probe microscopy of electronic transport in carbon nanotubes
128. Vertical scaling of single-wall carbon nanotube CMOS field effect transistors using top gate electrodes
129. 100 nm gate length high performance low power CMOS transistor structure
130. Electrical measurements of individual semiconducting single-walled carbon nanotubes of various diameters
131. Conductance spikes in single-walled carbon nanotube field-effect transistor
132. Single-wall nanotubes produced by metal-catalyzed disproportionation of carbon monoxide
133. Controlled production of aligned-nanotube bundles
134. Growth of a single freestanding multiwall carbon nanotube on each nanonickel dot
135. Growth of straight nanotubes with a cobalt-nickel catalyst by chemical vapor deposition
136. Self-oriented regular arrays of carbon nanotubes and their field emission properties
137. Highly-ordered carbon nanotube arrays for electronics applications
138. Growth of carbon nanotubes on cobalt disilicide precipitates by chemical vapor deposition
139. Controlled growth and electrical properties of heterojunctions of carbon nanotubes and silicon nanowires
140. Single-walled 4A carbon nanotube arrays
141. Single crystals of single-walled carbon nanotubes formed by self-assembly
142. CMOS with active well bias for low-power and RF/analog applications
143. Scalability and biasing strategy for CMOS with active well bias
144. Very small MOSFET's for low-temperature operation
145. Very high performance 50 nm CMOS at low temperature
146. Design considerations for CMOS near the limits of silicon
147. High performance of planar double gate MOSFETs with thin backgate dielectrics