Hierarchical power distribution with power tree in dozens of power domains for 90-nm low-power multi-CPU SoCs

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 1, 2007, Pages 74-82

  Kanno, Yusuke ^a,b   Mizuno, Hiroyuki ^a,b   Yasu, Yoshihiko ^c   Hirose, Kenji ^c   Shimazaki, Yasuhisa ^c   Hoshi, Tadashi ^c   Miyairi, Yujiro ^c   Ishii, Toshifumi ^b,c   Yamada, Tetsuya ^b   Irita, Takahiro ^c   Hattori, Toshihiro ^a,c   Yanagisawa, Kazumasa ^c   Irie, Naohiko ^b  

^a IEEE   (Japan)

^b HITACHI LTD   (Japan)

^c RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Common power domain; Fine grained power gating; Hierarchical power distribution; Leakage reduction; Low power; SoC

Indexed keywords

COMMON POWER DOMAIN; FINE-GRAINED POWER GATING; HIERARCHICAL POWER DISTRIBUTION; LEAKAGE REDUCTION; LOW POWER;

ELECTRIC POWER DISTRIBUTION; LEAKAGE CURRENTS; TREES (MATHEMATICS);

HIERARCHICAL SYSTEMS;

EID: 33846247851     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.885057     Document Type: Article

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