Application of advanced metal-oxide-semiconductor transistor in next generation, silicon resonant tunneling MOS transistor, to new logic circuit

Solid-State Electronics

Volumn 47, Issue 11, 2003, Pages 1969-1972

  Matsuo, Naoto ^a   Kihara, Hiroyuki ^a   Takami, Yoshinori ^a  

^a YAMAGUCHI UNIVERSITY   (Japan)

Author keywords

Logic circuit; Multi valued; SRTMOST

Indexed keywords

LOGIC CIRCUITS; RESONANT TUNNELING; SILICON;

DOUBLE-BARRIERS;

MOSFET DEVICES;

EID: 0043231406     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(03)00110-2     Document Type: Article

References (12)

1. Hisamoto D., Lee W.C., Kedzierski J., Anderson E., Takeuchi H., Asano K.et al. IEDM Tech. Dig. 1998;1032-1034.
2. Wong H.S.P., Frank D.J., Solomon P.M. IEDM Tech. Dig. 1998;407-410.
3. Timp G., Bude J., Bourdelle K.K., Garno J., Ghetti A., Gossmann H.et al. IEDM Tech. Dig. 1999;55-58.
4. Kawaura H, Sakamoto T, Baba T. Ext Abst 1999 Int Conf Solid State Devices and Materials 1999. p. 20.
5. Matsuo N., Miura T., Hamada H., Miyoshi T. Trans. IEICE-C. 81:1998;266.
6. Matsuo N., Miura T., Yamauchi J., Hamada H., Miyoshi T. Trans. IEICE-C. 82:1999;131.
7. Matsuo N., Kitagawa Y., Takami Y., Hamada H. Trans. IEICE-C. 84:2001;326.
8. Matsuo N., Yamauchi J., Kitagawa Y., Hamada H. Jpn. J. Appl. Phys. 39:2000;3850.
9. Matsuo N., Kitagawa Y., Takami Y., Yamauchi J. Superlattices Microstruct. 28:2000;407.
10. Omura Y. Perspective, science and technology for novel silicon on insulator devices. 1999;Kluwer Academic Publishers. p. 257.
11. Sakai T, Murakami K, Kawachi T. Ext Abst The Japan Society of Applied Physics 3p-k-9,672, 2000.
12. Matsuo N., Miura T., Urakami A., Miyoshi T. Jpn. J. Appl. Phys. 38:1999;3967.