Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 168-169

  Kinoshita, A ^a   Tsuchiya, Y ^a   Yagishita, A ^a   Uchida, K ^a   Koga, J ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC; CAPACITANCE; DOPING (ADDITIVES); INTERFACES (COMPUTER); ION IMPLANTATION; SCANNING ELECTRON MICROSCOPY; SCHOTTKY BARRIER DIODES; SEMICONDUCTOR JUNCTIONS;

DOPANT SEGREGATION (DS); SCHOTTKY BARRIER HEIGHT ENGINEERING; SCHOTTKY-SOURCE; SILICIDATION PROCESS;

MOSFET DEVICES;

EID: 4544244783     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2004.1345459     Document Type: Conference Paper

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