Spin transfer torque (STT)-MRAM - Based runtime reconfiguration FPGA circuit

Transactions on Embedded Computing Systems

Volumn 9, Issue 2, 2009, Pages 14-

  Zhao, Weisheng ^a   Belhaire, Eric ^a   Chappert, Claude ^a   Mazoyer, Pascale ^b  

^a UNIVERSITÉ PARIS SACLAY   (France)

^b STMICROELECTRONICS   (France)

Author keywords

Architecture; FPGA; Low power; MRAM; Multicontext; Nonvolatile; Runtime reconfiguration (RTR); Spin transfer torque (STT); System on Chip (SOC)

Indexed keywords

FPGA; LOW POWER; MRAM; MULTICONTEXT; NONVOLATILE; RUNTIME RECONFIGURATION (RTR); SPIN TRANSFER TORQUE (STT); SYSTEM ON CHIP (SOC);

DATA COMPRESSION; LEAKAGE CURRENTS; LOGIC DESIGN; MAGNETIC STORAGE; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; SPICE; SPIN DYNAMICS; STATIC RANDOM ACCESS STORAGE; SWITCHING CIRCUITS; TECHNOLOGY; TORQUE;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 70449421590     PISSN: 15399087     EISSN: 15583465     Source Type: Journal    
DOI: 10.1145/1596543.1596548     Document Type: Article

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