A New Route to Zero-Barrier Metal Source/Drain MOSFETs

IEEE Transactions on Nanotechnology

Volumn 3, Issue 1 SPEC. ISS., 2004, Pages 98-104

  Connelly, Daniel ^a   Faulkner, Carl ^a   Grupp, D E ^a   Harris, J S ^b  

^a Acorn Technologies   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

Nanotechnology; Schottky barriers; Schottky diodes; Schottky logic circuits; Schottky logic devices; Silicon on insulator (SOI) technology

Indexed keywords

COMPUTER SIMULATION; ELECTRIC INSULATORS; FERMI LEVEL; LOGIC DEVICES; NANOTECHNOLOGY; SCHOTTKY BARRIER DIODES; SILICON ON INSULATOR TECHNOLOGY; THERMIONIC POWER GENERATION;

CONTACT RESISTIVITY; SCHOTTKY BARRIERS; SCHOTTKY LOGIC CIRCUITS; SCHOTTKY LOGIC DEVICES;

MOSFET DEVICES;

EID: 2342457032     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2003.820774     Document Type: Conference Paper

References (23)

1. C. Wang, J. P. Snyder, and J. R. Tucker, "Sub-40 nm PtSi Schottky source/drain metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 74, no. 8, pp. 1174-1176, 1999.
2. J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, and C. Hu, "Complementary suicide source/drain thin-body MOSFET's for the 20 nm gate length regime," in IEEE IEDM Tech. Dig., 2000, pp. 57-60.
3. A. Itoh, M. Saitoh, and M. Asada, "A 25-nm-long channel metal-gate p-type Schottky source/drain metal-oxide-semiconductor field effect transistor on separation-by-implanted-oxygen substrate," Jpn. J. Appl. Phys., vol. 39, no. 8, pp. 4757-4758, Aug. 2000.
4. H.-C. Lin, M. F. Wang, F.-J. Hou, H.-N. Lin, C.-Y. Lu, J.-T. Liu, and T.-Y. Huang, "High-performance p-channel schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions," IEEE Electron Device Lett., vol. 24, pp. 102-104, Feb. 2003.
5. J. Guo and M. Lundstrom, "A computational study of thin-body, double gate, Schottky barrier MOSFETs," IEEE Trans. Electron Devices, vol. 49, pp. 1897-1902, Nov. 2002.
6. J. Kedzierski, M. Ieong, X. Peiqi, J. Bokor, T.-J. King, and C. Hu, "Design analysis of thin-body silicide source/drain devices," in Proc. IEEE Int. SOI Conf., 2001, pp. 21-22.
7. M. Jang, S. Lee, K. Kang, J. Oh, W. Cho, S. Maeng, W. Jung, T. Kang, J. Yang, and K. Im, "Schottky barrier tunnel transistor for nanometer regime applications," in Silicon Nanoelectronics Workshop Abstracts, June 2003, pp. 114-115.
8. Y.-C. Yeo, P. Ranade, Q. Lu, R. Lin, T.-J. King, and C. Hu, "Effect of high-k dielectrics on the workfunctions of metal and silicon gates," in IEEE Symp. VLSI Technology Tech. Dig., 2001, pp. 49-50.
9. Y.-C. Yeo, P. Ranade, T.-J. King, and C. Hu, "Effects of high-k gate dielectric materials on metal and silicon gate workfunctions," IEEE Electron Device Lett., vol. 23, pp. 342-344, June 2002.
10. DESSIS Version 8.5.5 User's Manual, ISE Corp., San Jose, CA, 2003.
11. M. K. Ieong, P. M. Solomon, S. E. Laux, H. S. P. Wong, and D. Chidambarrao, "Comparison of raised and Schottky source/drain MOSFET's using a novel tunneling contact model," in IEEE IEDM Tech. Dig., 1998, pp. 733-736.
12. J. Tersoff, "Schottky barrier heights and the continuum of gap states," Phys. Rev. Lett., vol. 52, no. 6, pp. 465-468, Feb. 6, 1984.
13. W. Mönch, "Role of virtual gap states and defects in metal-semiconductor contacts," Phys. Rev. Lett., vol. 58, no. 12, pp. 1260-1263, Mar. 23, 1987.
14. C. S. Rafferty, Z. Yu, B. Siegel, M. G. Ancona, J. Bude, and R. W. Dutton, "Multi-dimensional quantum effect simulation using a density-gradient model and script-level programming techniques," in Proc. IEEE SISPAD, 1998, pp. 137-140.
15. H. Shin, G. M. Yeric, A. F. Tasch, and C. M. Maziar, "Physically- based models for effective mobility and local-field mobility of electrons in MOS inversion layers," Solid State Electron., vol. 34, no. 6, pp. 545-552, 1991.
16. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFETs: Part I - effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, pp. 2357-2362, Dec. 1994.
17. S. Reggiani, M. Valdinoci, L. Colalongo, and G. Baccarani, "A unified analytical model for bulk and surface mobility in Si n- and p-channel MOSFETs," in Proc. ESSDERC, 1999, pp. 240-243.
18. J. D. Bude, "MOSFET modeling into the ballistic regime," in Proc. IEEE SISPAD, 2000, pp. 23-26.
19. "The international technology roadmap for semiconductors," Semiconductor Industry Assoc., http://public.itrs.net, 2001.
20. D. Connelly and M. Foisy, "Improved device technology evaluation and optimization," in Proc. IEEE SISPAD, 2000, pp. 155-158.
21. D. Connelly, C. Faulkner, and D. E. Grupp, "Optimizing Schottky S/D offset for 25 nm dual-gate CMOS performance," IEEE Electron Device Lett., vol. 24, pp. 411-413, June 2003.
22. _, "Performance advantage of metal source/drain in ultra-thin-body silicon-on-insulator and dual-gate CMOS," IEEE Trans. Electron Devices, vol. 50, pp. 1340-1345, May 2003.
23. D. Connelly, D. Grupp, and D. Yergeau, "Speed advantage of optimized metal S/D in 25 nm dual-gate fully-depleted CMOS," in Device Research Conf. Dig., Jun. 2002, pp. 77-78.