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Japanese Journal of Applied Physics

Volumn 49, Issue 9 PART 1, 2010, Pages

Nonvolatile delay flip-flop based on spin-transistor architecture and its power-gating applications

(2) Yamamoto, Shuu'ichirou a,b Sugahara, Satoshi a,b

a TOKYO INSTITUTE OF TECHNOLOGY (Japan)

b JAPAN SCIENCE AND TECHNOLOGY AGENCY (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DELAYS; ITS DATA; LAYOUT AREA; MAGNETIC TUNNEL JUNCTION; METAL OXIDE SEMICONDUCTOR; MOS-FET; MOSFETS; NON-VOLATILE; POWER-GATING; SHUT DOWN; TRANSISTOR ARCHITECTURE;

ARCHITECTURE; FLIP FLOP CIRCUITS; MAGNETIC STORAGE; MOS DEVICES; MOSFET DEVICES; SEMICONDUCTOR JUNCTIONS; TRANSISTORS; TUNNEL JUNCTIONS;

NONVOLATILE STORAGE;

EID: 78049361703 PISSN: 00214922 EISSN: 13474065 Source Type: Journal
DOI: 10.1143/JJAP.49.090204 Document Type: Article

Times cited : (39)

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