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Volumn , Issue , 2009, Pages 80-81

Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array

Author keywords

[No Author keywords available]

Indexed keywords

AREA REDUCTION; HYBRID PROCESS; HYBRID STRUCTURE; IN-FIELD; JUNCTION DEVICES; LOGIC-IN-MEMORY ARCHITECTURE; LOOK UP TABLE; METAL OXIDE SEMICONDUCTOR; NON-VOLATILE; PROGRAMMABLE LOGIC; SERIES CONNECTIONS; SPIN-INJECTION; STANDBY POWER;

EID: 70449359801     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (72)

References (4)
  • 4
    • 78650761039 scopus 로고    scopus 로고
    • M. Sekikawa, K. Kiyoyama, H. Hasegawa, K. Miura, T. Fukushima, S. Ikeda, T. Tanaka, H. Ohno, and M. Koyanagi, A Novel SPRAM (SPin-transfer torque RAM)-based Reconfigurable Logic Block for 3D-Stacked reconfigurable Spin Processor, Proc. of IEEE Intl. Electron Devices Meeting, IEDM2008, pp. 936-937, Dec. 2008.
    • M. Sekikawa, K. Kiyoyama, H. Hasegawa, K. Miura, T. Fukushima, S. Ikeda, T. Tanaka, H. Ohno, and M. Koyanagi, " A Novel SPRAM (SPin-transfer torque RAM)-based Reconfigurable Logic Block for 3D-Stacked reconfigurable Spin Processor," Proc. of IEEE Intl. Electron Devices Meeting, IEDM2008, pp. 936-937, Dec. 2008.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.