Nonvolatile magnetic flip-flop for standby-power-free SoCs

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2008, Pages 355-358

  Sakimura, Noboru ^a   Sugibayashi, Tadahiko ^a   Nebashi, Ryusuke ^a   Kasai, Naoki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FLIP FLOP CIRCUITS;

DESIGN LIBRARIES; FUNCTIONAL PERFORMANCES; LSI DESIGNS; MAXIMUM FREQUENCIES; NON VOLATILES; POWER DISSIPATIONS; TEST CHIPS;

INTEGRATED CIRCUITS;

EID: 57849093166     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2008.4672095     Document Type: Conference Paper

References (6)

1. J. Lee, et al.," Dynamic Voltage and Frequency Scaling (DVFS) Scheme for Multi-Domains Power Management," A-SSCC 2007, Nov. 2007, pp. 360-363.
2. K. Fukuoka, et al.," A 1.92μs-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors," Symp. VLSI Circuits, Jun. 2007, pp. 128-129.
3. S. Masui, et al.,"Design and applications of ferroelectric nonvolatile SRAM and flip-flop with unlimited read/program cycles and stable recall," CICC 2003, Sep. 2003, pp. 403-406.
4. W. Zhao, et al., "Integration of Spin-RAM technology in FPGA circuits," ICSICT '06, Oct. 2006, pp. 799-802.
5. H. Honjo, et al.,"Performance of write-line inserted MTJ for low-write-current MRAM cell," Journal of Applied Physics 103, 07A711, 2008.
6. N. Sakimura, et al.," A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture," A-SSCC 2007, Nov. 2007, pp. 216-219.