Microarchitectural techniques for power gating of execution units

Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04

Volumn , Issue , 2004, Pages 32-37

  Hu, Zhigang ^a   Buyuktosunoglu, Alper ^a   Srinivasan, Viji ^a   Zyuban, Victor ^a   Jacobson, Hans ^a   Bose, Pradip ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Execution units; Low power; Microarchitecture; Power gating

Indexed keywords

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LOGIC CIRCUITS; MATHEMATICAL MODELS; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE; TRANSISTORS;

EXECUTION UNITS; LOW POWER; MICROARCHITECTURE; POWER GATING;

MICROPROCESSOR CHIPS;

EID: 16244409255     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1013235.1013249     Document Type: Conference Paper

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