Power reduction techniques for an 8-core Xeon® processor

ESSCIRC 2009 - Proceedings of the 35th European Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 340-343

  Rusu, Stefan ^a   Tarn, Simon ^a   Muljono, Harry ^a   Stinson, Jason ^a   Ayers, David ^a   Chang, Jonathan ^a   Varada, Raj ^a   Ratta, Matt ^a   Kottapalli, Sailesh ^a   Vora, Sujal ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LONG CHANNEL DEVICES; MANAGEMENT TECHNIQUES; MANUFACTURING YIELD; MULTIPLE PRODUCTS; OPERATING POINTS; POWER CONSUMED; POWER CONSUMPTION; POWER CONVERSION EFFICIENCIES; POWER GATINGS; POWER REDUCTIONS; SILICON DIE; SLEEP MODE; THERMAL EVENTS; VOLTAGE DOMAINS;

CONVERSION EFFICIENCY; ELECTRIC POTENTIAL; MICROCONTROLLERS; VOLTAGE REGULATORS;

DIES;

EID: 72849146021     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2009.5326028     Document Type: Conference Paper

References (4)

1. K. Mistry, et al., "A 45nm Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging", IEDM Tech. Digest, December 2007
2. S. Rusu, et al., "A 45nm 8-Core Enterprise Xeon® Processor", ISSCC Tech. Digest, February 2009
3. F. Hamzaoglu, et al., "A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-K Metal-Gate CMOS Technology", ISSCC Tech. Digest, February 2008
4. R. Kumar, G. Hinton, "Nehalem: a family of 45 nm IA processors", ISSCC Tech. Digest, February 2009