LAP: A logic activity packing methodology for leakage power-tolerant FPGAs

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2005, Pages 257-262

  Hassan, Hassan ^a   Anis, Mohab ^a   Elmasry, Mohamed ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Activity profile; Basic Logic Elements (BLE); Configurable Logic Blocks (CLB); FPGA; Leakage power; Packing; Sleep transistor (ST)

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; FIELD PROGRAMMABLE GATE ARRAYS; LEAKAGE CURRENTS; LOGIC DESIGN; MODIFICATION; POWER ELECTRONICS;

BASIC LOGIC ELEMENTS (BLE); CONFIGURABLE LOGIC BLOCKS (CLB); LEAKAGE POWER;

ELECTRONICS PACKAGING;

EID: 28444460460     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2005.195524     Document Type: Conference Paper

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