Leakage power Reduction for coarse grained dynamically reconfigurable processor arrays with fine grained power Gating technique

Proceedings of the 2008 International Conference on Field-Programmable Technology, ICFPT 2008

Volumn , Issue , 2008, Pages 329-332

  Saito, Yoshiki ^a,b   Shirai, Tomoaki ^a,b   Nakamura, Takuro ^a,b   Nishimura, Takashi ^a,b   Hasegawa, Yohei ^a,b   Tsutsumi, Satoshi ^a,b   Kashima, Toshihiro ^a,b   Nakata, Mitsutaka ^a,b   Takeda, Seidai ^a,b   Usami, Kimiyoshi ^a,b   Amano, Hideharu ^a,b  

^a KEIO UNIVERSITY   (Japan)

^b SHIBAURA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION;

ADVANCED PROCESS; AREA OVERHEADS; CLOCK FREQUENCIES; COARSE-GRAINED; CONTROL MODES; DYNAMIC POWER CONSUMPTION; DYNAMICALLY RECONFIGURABLE PROCESSORS; FINE-GRAINED POWER; INDIVIDUAL-BASED; LAYOUT DESIGNS; LEAKAGE POWER; LEAKAGE POWER REDUCTIONS; PROCESSING ELEMENTS; RE-CONFIGURABLE; REAL APPLICATIONS; TOTAL POWER CONSUMPTION;

LEAKAGE CURRENTS;

EID: 63049088417     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2008.4762410     Document Type: Conference Paper

References (8)

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