True energy-performance analysis of the MTJ-based logic-in-memory architecture (1-bit full adder)

IEEE Transactions on Electron Devices

Volumn 57, Issue 5, 2010, Pages 1023-1028

  Ren, Fengbo ^a   Marković, Dejan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Adders; Complimentary metal oxide semiconductor (CMOS) digital integrated circuits; Energy delay tradeoff; Magnetic tunnel junction (MTJ) logic; Spin transfer torque (STT) devices

Indexed keywords

COMPLIMENTARY METAL OXIDE SEMICONDUCTORS; COMPLIMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DIGITAL INTEGRATED CIRCUITS; MAGNETIC TUNNEL JUNCTION; SPIN TRANSFER TORQUE; SPIN-TRANSFER TORQUE (STT) DEVICES;

ADDERS; CMOS INTEGRATED CIRCUITS; COMMUNICATION CHANNELS (INFORMATION THEORY); DELAY CIRCUITS; DIELECTRIC DEVICES; DIGITAL DEVICES; DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; MAGNETIC DEVICES; SEMICONDUCTOR JUNCTIONS; SPIN DYNAMICS; SWITCHING CIRCUITS; TUNNEL JUNCTIONS; WIND TUNNELS;

LOGIC CIRCUITS;

EID: 77951622781     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2043389     Document Type: Article

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