Overview and status of metal S/D Schottky-barrier MOSFET technology

IEEE Transactions on Electron Devices

Volumn 53, Issue 5, 2006, Pages 1048-1058

  Larson, John M ^a   Snyder, John P ^a  

^a Spinnaker Semiconductor   (United States)

Author keywords

CMOSFETs; Erbium silicide; Metal source drain (S D); Platinum silicide; Schottky barriers (SBs); Short channel MOSFET; Transistors

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); LEAKAGE CURRENTS; SCHOTTKY BARRIER DIODES; SEMICONDUCTING SILICON; SUBSTRATES;

ERBIUM SILICIDE; METAL DRAIN; METAL SOURCE; PLATINUM SILICIDE; SCHOTTKY POTENTIAL BARRIER; SHORT-CHANNEL MOSFET;

MOSFET DEVICES;

EID: 33646042498     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.871842     Document Type: Review

References (62)

1. "Front end processes," in International Technology Roadmap for Semiconductors 2003 Edition. Austin, TX: Semiconductor Industry Assoc., 2003.
2. Y. Nishi, "Insulated gate field effect transistor and its manufacturing method," Patent 587 527, 1970.
3. M. P. Lepselter and S. M. Sze, "SB-IGFET: An insulated-gate field-effect transistor using Schottky barrier contacts for source and drain," Proc. IEEE, vol. 56, no. 8, pp. 1400-1402, Aug. 1968.
4. C. J. Koeneke, S. M. Sze, R. M. Levin, and E. Kinsbron, "Schottky MOSFET for VLSI," in IEDM Tech. Dig., 1981, pp. 367-370.
5. C. J. Koeneke and W. T. Lynch, "Lightly doped Schottky MOSFET," in IEDM Tech. Dig., 1982, pp. 466-469.
6. T. Mochizuki and K. D. Wise, "An n-channel MOSFET with Schottky source and drain," IEEE Electron Device Lett., vol. EDL-5, no. 4, pp. 108-111, Apr. 1984.
7. S. E. Swirhun, E. Sangiorgi, A. J. Weeks, R. M. Swanson, K. C. Saraswat, and R. W. Dutton, "A VLSI-suitable Schottky-barrier CMOS process," IEEE Trans. Electron Devices, vol. ED-32, no. 2, pp. 194-202, Feb. 1985.
8. C. S. Oh, Y. H. Koh, and C. K. Kim, "A new P-Channel MOSFET structure with Schottky-Clamped source and drain," in IEDM Tech. Dig., 1984, pp. 609-612.
9. B.-Y. Tsui and M.-C. Chen, "A novel process for high-performance Schottky barrier PMOS," J. Electrochem. Soc., vol. 136, no. 5, pp. 1456-1459, May 1989.
10. M. Kimura and T. Matsudate, "A new type of Schottky tunnel transistor," IEEE Electron Device Lett., vol. 15, no. 10, pp. 412-414, Oct. 1994.
11. M. Sugino, L. A. Akers, and M. E. Rebeschini, "CMOS latch-up elimination using Schottky barrier PMOS," in IEDM Tech. Dig., 1982, pp. 462-465.
12. M. Sugino, L. A. Akers, and M. E. Rebeschini, "Latchup-free Schottky-barrier CMOS," IEEE Trans. Electron Devices, vol. ED-30, no. 2, pp. 110-118, Feb. 1983.
13. J. R. Tucker, C. Wang, and P. S. Carney, "Silicon field-effect transistor based on quantum tunneling," Appl. Phys. Lett., vol. 65, no. 5, pp. 618-620, Aug. 1994.
14. J. R. Tucker, C. Wang, J. W. Lyding, T.-C. Shen, and G. C. Abeln, "Nanometer scale MOSFETs and STM paterning on Si," in Proc. Int. Conf. Solid State Devices Mater., 1994, pp. 322-324.
15. J. P. Snyder, "The physics and technology of platinum silicide source and drain field effect transistors," Ph.D. dissertation, Stanford Univ., Stanford, CA, 1996.
16. J. Kedzierski, P. Xuan, V. Subramanian, J. Bokor, T.-J. King, C. Hu, and E. Anderson, "A 20 nm gate-length ultra-thin body p-MOSFET with silicide S/D," Superlattices Microstruct., vol. 28, no. 5/6, pp. 445-452, 2000.
17. E. Dubois and G. Larrieu, "Measurement of low Schottky barrier heights applied to S/D metal-oxide-semiconductor field effect transistors," J. Appl. Phys., vol. 96, no. 1, pp. 729-737, Jul. 2004.
18. V. W. L. Chin, J. W. V. Storey, and M. A. Green, "Characteristics of p-type PtSi Schottky diodes under reverse bias," J. Appl. Phys., vol. 68, pp. 4127-4132, Oct. 1990.
19. S. Zhu, J. Chen, M.-F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, C. H. Tung, A. Chin, and D. L. Kwong, "N-type Schottky barrier S/D MOSFET using Ytterbium silicide," IEEE Electron Device Lett., vol. 25, no. 8, pp. 565-567, Aug. 2004.
20. M. Jang, Y. Kim, J. Shin, and S. Lee, "Characterization of erbium-silicided Schottky diode junction," IEEE Electron Device Lett., vol. 26, no. 6, pp. 354-356, Jun. 2005.
21. T = 280 GHz," IEEE Electron Device Lett., vol. 25, no. 4, pp. 220-222, Apr. 2004.
22. J. Kedzierski, P. Xuan, E. H. Anderson, J. Bokor, T.-J. King, and C. Hu, "Complementary silicide S/D thin-body MOSFETs for the 20 nm gate length regime," in IEDM Tech. Dig., 2000, pp. 57-60.
23. B.-Y. Tsui and C.-P. Lin, "A novel 25-nm modified Schottky-barrier FinFET with high performance," IEEE Electron Device Lett., vol. 25, no. 6, pp. 430-432, Jun. 2004.
24. D. Connelly, C. Faulkner, and D. E. Grupp, "Optimizing Schottky S/D offset for 25-nm dual-gate CMOS performance," IEEE Electron Device Lett., vol. 24, no. 6, pp. 411-413, Jun. 2003.
25. A. Itoh, M. Saitoh, and M. Asada, "A 25-nm-long channel metal-gate p-type Schottky S/D metal-oxide-semiconductor field effect transistor on separation-by-implanted-oxygen substrate," Jpn. J. Appl. Phys., vol. 39, no. 8, pp. 4757-4758, Aug. 2000.
26. M. Jang, Y. Kim, J. Shin, S. Lee, and K. Park, "A 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistor," Appl. Phys. Lett., vol. 84, no. 5, pp. 741-743, Feb. 2004.
27. W. Saitoh, A. Itoh, S. Yamagami, and M. Asada, "Analysis of short-channel Schottky S/D metal-oxide-semiconductor field-effect transistor on silicon-on insulator substrate and demonstration of sub-50-nm n-type devices and metal gate," Jpn. J. Appl. Phys., vol. 38, no. 11, pp. 6226-6231, Nov. 1999.
28. H. Sato, H. Sato, T. Iguchi, and M. Asada, "Increase drive current by Pt/W protection on short-channel Schottky S/D metal-oxide-semiconductor field-effect transistors with metal gate," Jpn. J. Appl. Phys., vol. 43, no. 9A, pp. 6038-6039, 2004.
29. 2 using oxidation in a local stress field and fabrication of nanometer metal-oxide-semiconductor field-effect transistors," J. Appl. Phys., vol. 96, no. 10, pp. 5775-5780, Nov. 2004.
30. S. Matsumoto, M. Nishisaka, and T. Asano, "CMOS application of Schottky S/D SOI MOSFET with shallow doped extension," Jpn. J. Appl. Phys., vol. 43, no. 4B, pp. 2170-2175, 2004.
31. M. Nishisaka, S. Matsumoto, and T. Asano, "Schottky S/D SOI MOSFET with shallow doped extension," Jpn. J. Appl. Phys., vol. 42, no. 4B, pp. 2009-2013, Apr. 2003.
32. G. Larrieu and E. Dubois, "Schottky-barrier S/D MOSFETs on ultrathin SOI body with a tungsten metallic midgap gate," IEEE Electron Device Lett., vol. 25, no. 12, pp. 801-803, Dec. 2004.
33. W. Saitoh, S. Yamagami, A. Itoh, and M. Asada, "35 nm metal gate SOI-p-MOSFETs with PtSi Schottky S/D," in Proc. Device Res. Conf., 1999, pp. 30-31.
34. S. Y. Zhu, H. Y. Hu, J. D. Chen, S. J. Whang, J. H. Chen, C. Shen, C. X. Zhu, S. J. Lee, M. F. Li, and D. S. H. Chan et al., "Low temperature MOSFET technology with Schottky barrier S/D, high-k gate dielectric and metal gate electrode," Solid State Electron., vol. 48, no. 10/11, pp. 1987-1992, Oct./Nov. 2004.
35. A. Kinoshita, C. Tanaka, K. Uchida, and J. Koga, "High-performance 50-nm-gate-length Schottky-S/D MOSFETs with dopant-segregation junctions," in VLSI Symp. Tech. Dig., 2005, pp. 158-159.
36. A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, and J. Koga, "Solution for high-performance Schottky-S/D MOSFETs: Schottky barrier height engineering with dopant segregation technique," in VLSI Symp. Tech. Dig., 2004, pp. 168-169.
37. B.-Y. Tsui and C.-P. Lin, "Process and characteristics of modified Schottky barrier (MSB) p-channel FinFETs," IEEE Trans. Electron Devices, vol. 52, no. 11, pp. 2455-2462, Nov. 2005.
38. M. Tao, D. Udeshi, S. Agarwal, E. Maldonado, and W. P. Kirk, "Negative Schottky barrier between titanium and n-type Si(001) for low-resistance ohmic contacts," Solid State Electron., vol. 48, no. 2, pp. 335-338, Feb. 2004.
39. E. H. Rhoderick and R. H. Williams, "Metal-semiconductor contacts," in Monographs in Electrical and Electronic Engineering, 2nd ed. P. Hammond and R. L. Grimsdale, Eds. Oxford, U.K.: Clarendon, 1988.
40. S. Zhu, R. Li, S. J. Lee, M. F. Li, A. Du, J. Singh, C. Zhu, A. Chin, and D. L. Kwong, "Germanium pMOSFETs with Schottky-barrier germanide S/ D, high-K gate dielectric and metal gate," IEEE Electron Device Lett., vol. 26, no. 2, pp. 81-83, Feb. 2005.
41. M. Fritze, R. Mallen, B. Wheeler, D. Yost, J. P. Snyder, B. Kasprowicz, B. Eynon, and H. Y. Liu, "Limits of strong phase shift patterning for device research," in Proc. SPIE - Optical Microlithography XVI, 2003, pp. 327-343.
42. R. Hattori, A. Nakae, and J. Shirafuji, "A new type of tunnel-effect transistor employing internal field emission of Schottky barrier junction," Jpn. J. Appl. Phys., vol. 31, no. 10B, pp. L1467-L1469, Oct. 1992.
43. R. Hattori and J. Shirafuji, "Numerical simulation of tunnel effect transistor employing internal field emission of Schottky barrier junction," Jpn. J. Appl. Phys. 1, Regul. Rap. Short Notes, vol. 33, no. 1B, pp. 612-618, Jan. 1994.
44. F. A. Padovani and R. Stratton, "Field and thermionic-field emission in Schottky barriers," Solid State Electron., vol. 9, no. 7, pp. 695-707, Jul. 1966.
45. M. Ieong, P. M. Solomon, S. E. Laux, W.-S. P. Wong, and D. Chidambarrao, "Comparison of raised and Schottky S/D MOSFETs using a novel tunneling contact model," in IEDM Tech. Dig., 1998, pp. 733-736.
46. J. Knoch and J. Appenzeller, "Impact of the channel thickness on the performance of Schottky barrier metal-on-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 81, no. 16, pp. 3082-3084, Oct. 2002.
47. B. Winstead and U. Ravaioli, "Simulation of Schottky barrier MOSFETs with a coupled quantum injection/Monte Carlo technique," IEEE Trans. Electron Devices, vol. 47, no. 6, pp. 1241-1246, Jun. 2000.
48. International Technology Roadmap for Semiconductors 2004 Update. Austin, TX: Semiconductor Industry Assoc., 2004.
49. International Technology Roadmap for Semiconductors 2002 Update. Austin, TX: Semiconductor Industry Assoc., 2002.
50. International Technology Roadmap for Semiconductors 2000 Update. Austin, TX: Semiconductor Industry Assoc., 2000.
51. S. A. Rishton, K. Ismail, J. O. Chu, K. K. Chan, and K. Y. Lee, "New complimentary metal-oxide semiconductor technology with self-aligned Schottky S/D and low-resistance T gates," J. Vac. Sci. Technol. B, Microelectron. Process. Phenom., vol. 15, no. 6, pp. 2795-2798, Nov. 1997.
52. K. Uchida, K. Matsuzawa, J. Koga, S. Takagi, and A. Toriumi, "Enhancement of hot-electron generation rate in Schottky source metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 76, no. 26, pp. 3992-3994, Jun. 2000.
53. M. Sugino, L. A. Akers, and M. E. Rebeschini, "Latchup-free Schottky-barrier CMOS," IEEE Trans. Electron Devices, vol. ED-30, no. 2, pp. 110-118, Feb. 1983.
54. T. Iwamoto, T. Ogura, M. Terai, H. Watanebe, H. Watanabe, N. Ikarashi, M. Miyamura, T. Tatsumi, M. Saitoh, and A. Morioka et al., "A highly manufacturable low power high speed HfSiO CMOS FET with dual poly-Si gate electrodes," in IEDM Tech. Dig., 2003, pp. 27.5.1-27.5.4.
55. S. S. Mukherjee, J. Emer, and S. K. Reinhardt, "The soft error problem: An architectural perspective," in Proc. 11th Int. Symp. HPCA-11, 2005, p. 5.
56. C. Wang, J. P. Snyder, and J. R. Tucker, "Sub-40 nm PtSi Schottky S/D metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 74, no. 8, pp. 1174-1176, Feb. 1999.
57. J. Kedzierski, M. Leong, P. Xuan, J. Bokor, T.-J. King, and C. Hu, "Design analysis of thin-body silicide S/D devices," in Proc. IEEE Int. SOI Conf., 2001, pp. 21-22.
58. M. Tao, D. Udeshi, S. Agarwal, N. Basit, E. Maldonado, and W. P. Kirk, "Low Schottky barrier on N-type Si for N-channel Schottky S/D MOSFET's," in Mater. Res. Soc. Symp. Proc., 2003, pp. 297-302.
59. D. Connelly, C. Faulkner, D. E. Grupp, and J. S. Harris, "A new route to zero-barrier metal S/D MOSFETs," IEEE Trans. Nanotechnol., vol. 3, no. 1, pp. 98-104, Mar. 2004.
60. J. Guo and M. Lundstrom, "A computational study of thin-body, double-gate, Schottky barrier MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 1897-1902, Nov. 2002.
61. S. Xiong, T.-J. King, and J. Bokor, "A comparison study of symmetric ultrathin-body double-gate devices with metal S/D and doped S/D," IEEE Trans. Electron Devices, vol. 52, no. 8, pp. 1859-1867, Aug. 2005.
62. K. Ikeda, Y. Yamashita, A. Endoh, T. Fukano, K. Hikosaka, and T. Mimura, "50-nm gate Schottky S/D p-MOSFETs with a SiGe channel," IEEE Electron Device Lett., vol. 23, no. 11, pp. 670-672, Nov. 2002.