-
1
-
-
4444272791
-
Design and reliability challenges in nanometer technologies
-
S. Borkar, "Design and reliability challenges in nanometer technologies," in Proc. ACM/IEEE Design Autom. Conf., 2004, p. 75.
-
(2004)
Proc. ACM/ IEEE Design Autom. Conf.
, pp. 75
-
-
Borkar, S.1
-
2
-
-
66649124356
-
Managing process variation in Intels 45 nm CMOS technology
-
June
-
K. Kuhn, C. Kenyon, A. Kornfeld, M. Liu, A. Maheshwari, W. Shih, S. Sivakumar, G. Taylor, P. VanDerVoorn, and K. Zawadzki, "Managing process variation in Intels 45 nm CMOS technology," Intel Technol. J., vol. 12, June 2008.
-
(2008)
Intel Technol. J.
, vol.12
-
-
Kuhn, K.1
Kenyon, C.2
Kornfeld, A.3
Liu, M.4
Maheshwari, A.5
Shih, W.6
Sivakumar, S.7
Taylor, G.8
VanDerVoorn, P.9
Zawadzki, K.10
-
3
-
-
0032028948
-
Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFET's: Uniformity, reliability, and dopant penetration of the gate oxide
-
PII S0018938398016712
-
H. S. Momose, S.-I. Nakamura, T. Ohguro, T. Yoshitomi, E. Morifuji, T. Morimoto, Y. Katsumata, and H. Iwai, "Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: Uniformity, reliability, and dopant penetration of the gate oxide," IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 691-700, Mar. 1998. (Pubitemid 128736601)
-
(1998)
IEEE Transactions on Electron Devices
, vol.45
, Issue.3
, pp. 691-700
-
-
Momose, H.S.1
Nakamura, S.-I.2
Ohguro, T.3
Yoshitomi, T.4
Morifuji, E.5
Morimoto, T.6
Katsumata, Y.7
Iwai, H.8
-
4
-
-
0024754187
-
Matching properties of MOS transistors
-
Oct.
-
M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, Oct. 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 1433-1440
-
-
Pelgrom, M.J.M.1
Duinmaijer, A.C.J.2
Welbers, A.P.G.3
-
5
-
-
0346778721
-
Statistical timing analysis considering spatial correlations using a single PERT-like traversal
-
H. Chang and S. S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single PERT-like traversal," in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, 2003, pp. 621-625.
-
(2003)
Proc. IEEE/ACM Int. Conf. on Computer-Aided Design
, pp. 621-625
-
-
Chang, H.1
Sapatnekar, S.S.2
-
6
-
-
84954410406
-
Statistical delay computation considering spatial correlations
-
Jan.
-
A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda, "Statistical delay computation considering spatial correlations," in Proc. Asia/South Pacific Design Autom. Conf., Jan. 2003, pp. 271-276.
-
(2003)
Proc. Asia/South Pacific Design Autom. Conf.
, pp. 271-276
-
-
Agarwal, A.1
Blaauw, D.2
Zolotov, V.3
Sundareswaran, S.4
Zhao, M.5
Gala, K.6
Panda, R.7
-
7
-
-
49549101062
-
Static timing: Back to our roots
-
Jan.
-
R. Chen, L. Zhang, V. Zolotov, C. Visweswariah, and J. Xiong, "Static timing: Back to our roots," in Proc. Asia/South Pacific Design Autom. Conf., Jan. 2008, pp. 310-315.
-
(2008)
Proc. Asia/South Pacific Design Autom. Conf.
, pp. 310-315
-
-
Chen, R.1
Zhang, L.2
Zolotov, V.3
Visweswariah, C.4
Xiong, J.5
-
8
-
-
34547152233
-
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits
-
DOI 10.1145/1146909.1147109, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06
-
S. Bhardwaj, S. Vrudhula, P. Ghanta, and Y. Cao, "Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits," in Proc. ACM/IEEE Design Autom. Conf., July 2006, pp. 791-796. (Pubitemid 47114001)
-
(2006)
Proceedings - Design Automation Conference
, pp. 791-796
-
-
Bhardwaj, S.1
Vrudhula, S.2
Ghanta, P.3
Cao, Y.4
-
9
-
-
33947594386
-
Robust extraction of spatial correlation
-
DOI 10.1109/TCAD.2006.884403
-
J. Xiong, V. Zolotov, and L. He, "Robust extraction of spatial correlation," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, pp. 619-631, Apr. 2007. (Pubitemid 46479737)
-
(2007)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.26
, Issue.4
, pp. 619-631
-
-
Xiong, J.1
Zolotov, V.2
He, L.3
-
10
-
-
34547268011
-
A general framework for spatial correlation modeling in VLSI design
-
DOI 10.1109/DAC.2007.375277, 4261296, 2007 44th ACM/IEEE Design Automation Conference, DAC'07
-
F. Liu, "A general framework for spatial correlation modeling in VLSI design," in Proc. ACM/IEEE Design Autom. Conf., San Diego, CA, 2007, pp. 817-822. (Pubitemid 47130078)
-
(2007)
Proceedings - Design Automation Conference
, pp. 817-822
-
-
Liu, F.1
-
11
-
-
20344385187
-
-
Boston, MA: Springer
-
S. S. Sapatnekar, Timing. Boston, MA: Springer, 2004.
-
(2004)
Timing
-
-
Sapatnekar, S.S.1
-
13
-
-
27644526873
-
Statistical timing analysis under spatial correlations
-
DOI 10.1109/TCAD.2005.850834
-
H. Chang and S. S. Sapatnekar, "Statistical timing analysis under spatial correlations," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, pp. 1467-1482, Sept. 2005. (Pubitemid 41558372)
-
(2005)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.24
, Issue.9
, pp. 1467-1482
-
-
Chang, H.1
Sapatnekar, S.S.2
-
14
-
-
0001310038
-
The greatest of a finite set of random variables
-
Mar.-Apr.
-
C. Clark, "The greatest of a finite set of random variables," Oper. Res., vol. 9, pp. 85-91, Mar.-Apr. 1961.
-
(1961)
Oper. Res.
, vol.9
, pp. 85-91
-
-
Clark, C.1
-
15
-
-
16244393708
-
Asymptotic probability extraction for non-normal distributions of circuit performance
-
1A.1, ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
-
X. Li, J. Le, P. Gopalakrishnan, and L. T. Pileggi, "Asymptotic probability extraction for non-normal distributions of circuit performance," in Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design, 2004, pp. 2-9. (Pubitemid 40449206)
-
(2004)
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
, pp. 2-9
-
-
Li, X.1
Le, J.2
Gopalakrishnan, P.3
Pileggi, L.T.4
-
16
-
-
33846193172
-
Asymptotic probability extraction for nonnormal performance distributions
-
DOI 10.1109/TCAD.2006.882593
-
X. Li, J. Le, P. Gopalakrishnan, and L. T. Pileggi, "Asymptotic probability extraction for nonnormal performance distributions," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, pp. 16-37, Jan. 2007. (Pubitemid 46103916)
-
(2007)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.26
, Issue.1
, pp. 16-37
-
-
Li, X.1
Le, J.2
Gopalakrishnan, P.3
Pileggi, L.T.4
-
17
-
-
27944484450
-
Correlation-aware statistical timing analysis with non-gaussian delay distributions
-
7.2, Proceedings 2005, 42nd Design Automation Conference, DAC 2005
-
Y. Zhan, A. Strojwas, X. Li, and L. Pileggi, "Correlation-aware statistical timing analysis with non-Gaussian delay distributions," in Proc. ACM/IEEE Design Autom. Conf., 2005, pp. 77-82. (Pubitemid 41675405)
-
(2005)
Proceedings - Design Automation Conference
, pp. 77-82
-
-
Zhan, Y.1
Strojwas, A.J.2
Li, X.3
Pileggi, L.T.4
Newmark, D.5
Sharma, M.6
-
18
-
-
34547223772
-
Statistical timing analysis with correlated non-gaussian parameters using independent component analysis
-
DOI 10.1145/1146909.1146953, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06
-
J. Singh and S. S. Sapatnekar, "Statistical timing analysis with correlated non-Gaussian parameters using independent component analysis," in Proc. ACM/IEEE Design Autom. Conf., 2006, pp. 155-160. (Pubitemid 47113885)
-
(2006)
Proceedings - Design Automation Conference
, pp. 155-160
-
-
Singh, J.1
Sapatnekar, S.2
-
19
-
-
37249034691
-
A scalable statistical static timing analyzer incorporating correlated non-Gaussian and Gaussian parameter variations
-
DOI 10.1109/TCAD.2007.907241
-
J. Singh and S. S. Sapatnekar, "A scalable statistical static timing analyzer incorporating correlated non-Gaussian and Gaussian parameter variations," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 1, pp. 160-173, Jan. 2008. (Pubitemid 350281175)
-
(2008)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.27
, Issue.1
, pp. 160-173
-
-
Singh, J.1
Sapatnekar, S.S.2
-
20
-
-
0042826822
-
Independent component analysis: Algorithms and applications
-
DOI 10.1016/S0893-6080(00)00026-5, PII S0893608000000265
-
A. Hyvärinen and E. Oja, "Independent component analysis: Algorithms and applications," Neural Netw., vol. 13, pp. 411-430, 2000. (Pubitemid 30447427)
-
(2000)
Neural Networks
, vol.13
, Issue.4-5
, pp. 411-430
-
-
Hyvarinen, A.1
Oja, E.2
-
21
-
-
27944511054
-
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
-
7.1, Proceedings 2005, 42nd Design Automation Conference, DAC 2005
-
H. Chang, V. Zolotov, S. Narayan, and C. Visweswariah, "Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions," in Proc. ACM/IEEE Design Autom. Conf., 2005, pp. 71-76. (Pubitemid 41675404)
-
(2005)
Proceedings - Design Automation Conference
, pp. 71-76
-
-
Chang, H.1
Zolotov, V.2
Narayan, S.3
Visweswariah, C.4
-
22
-
-
27944484876
-
A general framework for accurate statistical timing analysis considering correlations
-
7.4, Proceedings 2005, 42nd Design Automation Conference, DAC 2005
-
V. Khandelwal and A. Srivastava, "A general framework for accurate statistical timing analysis considering correlations," in Proc. ACM/ IEEE Design Autom. Conf., 2005, pp. 89-94. (Pubitemid 41675407)
-
(2005)
Proceedings - Design Automation Conference
, pp. 89-94
-
-
Khandelwal, V.1
Srivastava, A.2
-
23
-
-
34047175379
-
A quadratic modeling-based framework for accurate statistical timing analysis considering correlations
-
DOI 10.1109/TVLSI.2007.893585
-
V. Khandelwal and A. Srivastava, "A quadratic modeling-based framework for accurate statistical timing analysis considering correlations," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, pp. 206-215, Feb. 2007. (Pubitemid 46527353)
-
(2007)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.15
, Issue.2
, pp. 206-215
-
-
Khandelwal, V.1
Srivastava, A.2
-
24
-
-
34547254653
-
Non-linear statistical static timing analysis for non-Gaussian variation sources
-
DOI 10.1109/DAC.2007.375162, 4261181, 2007 44th ACM/IEEE Design Automation Conference, DAC'07
-
L. Cheng, J. Xiong, and L. He, "Non-linear statistical static timing analysis for non-Gaussian variation sources," in Proc. ACM/IEEE Design Autom. Conf., 2007, pp. 250-255. (Pubitemid 47129963)
-
(2007)
Proceedings - Design Automation Conference
, pp. 250-255
-
-
Cheng, L.1
Xiong, J.2
He, L.3
-
25
-
-
33847759065
-
A yield model for integrated circuits and its application to statistical timing analysis
-
DOI 10.1109/TCAD.2006.883924
-
F. N. Najm, N. Menezes, and I. A. Ferzli, "A yield model for integrated circuits and its application to statistical timing analysis," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, pp. 574-591, Mar. 2007. (Pubitemid 46375764)
-
(2007)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.26
, Issue.3
, pp. 574-591
-
-
Najm, F.N.1
Menezes, N.2
Ferzli, I.A.3
-
26
-
-
46149095291
-
A linear-time approach for static timing analysis covering all process corners
-
S. Onaissi and F. N. Najm, "A linear-time approach for static timing analysis covering all process corners," in Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design, 2006, pp. 217-224.
-
(2006)
Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design
, pp. 217-224
-
-
Onaissi, S.1
Najm, F.N.2
-
28
-
-
0041589378
-
Analysis and minimization techniques for total leakage considering gate oxide leakage
-
Jun.
-
D. Lee, W. Kwong, D. Blaauw, and D. Sylvester, "Analysis and minimization techniques for total leakage considering gate oxide leakage," in Proc. ACM/IEEE Design Autom. Conf., Jun. 2003, pp. 175-180.
-
(2003)
Proc. ACM/IEEE Design Autom. Conf.
, pp. 175-180
-
-
Lee, D.1
Kwong, W.2
Blaauw, D.3
Sylvester, D.4
-
29
-
-
1542269365
-
Statistical estimation of leakage current considering inter- and intra-die process variation
-
Aug.
-
R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester, "Statistical estimation of leakage current considering inter- and intra-die process variation," in Proc. Int. Symp. Low Power Electronic Devices, Aug. 2003, pp. 84-89.
-
(2003)
Proc. Int. Symp. Low Power Electronic Devices
, pp. 84-89
-
-
Rao, R.1
Srivastava, A.2
Blaauw, D.3
Lee, D.X.4
-
30
-
-
4444351567
-
Parametric yield estimation considering leakage variability
-
Jun.
-
R. Rao, A. Devgan, D. Blaauw, and D. Sylvester, "Parametric yield estimation considering leakage variability," in Proc. ACM/IEEE Design Autom. Conf., Jun. 2004, pp. 442-447.
-
(2004)
Proc. ACM/ IEEE Design Autom. Conf.
, pp. 442-447
-
-
Rao, R.1
Devgan, A.2
Blaauw, D.3
Sylvester, D.4
-
32
-
-
0028583468
-
Comparison of methods of computing correlated lognormal sum distributions and outages for digital wireless applications
-
Jun.
-
A. A. Abu-Dayya and N. C. Beaulieu, "Comparison of methods of computing correlated lognormal sum distributions and outages for digital wireless applications," in IEEE 44th Veh. Technol. Conf., Jun. 1994, vol. 1, pp. 175-179.
-
(1994)
IEEE 44th Veh. Technol. Conf.
, vol.1
, pp. 175-179
-
-
Abu-Dayya, A.A.1
Beaulieu, N.C.2
-
33
-
-
27944470947
-
Full-chip analysis of leakage power under process variations, including spatial correlations
-
32.1, Proceedings 2005, 42nd Design Automation Conference, DAC 2005
-
H. Chang and S. S. Sapatnekar, "Full-chip analysis of leakage power under process variations, including spatial correlations," in Proc. ACM/ IEEE Design Autom. Conf., Anaheim, CA, Jun. 2005, pp. 523-528. (Pubitemid 41675492)
-
(2005)
Proceedings - Design Automation Conference
, pp. 523-528
-
-
Chang, H.1
Sapatnekar, S.S.2
-
34
-
-
27944464454
-
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance
-
32.3, Proceedings 2005, 42nd Design Automation Conference, DAC 2005
-
A. Srivastava, S. Shah, K. Agarwal, D. Sylvester, D. Blaauw, and S. W. Director, "Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance," in Proc. ACM/IEEE Design Autom. Conf., Jun. 2005, pp. 535-540. (Pubitemid 41675494)
-
(2005)
Proceedings - Design Automation Conference
, pp. 535-540
-
-
Srivastava, A.1
Shah, S.2
Agarwal, K.3
Sylvester, D.4
Blaauw, D.5
Director, S.6
-
35
-
-
34248335446
-
Prediction of leakage power under process uncertainties
-
Apr. Art. (27 pages)
-
H. Chang and S. S. Sapatnekar, "Prediction of leakage power under process uncertainties," ACM Trans. Design Autom. Electron. Syst., vol. 12, Apr. 2007, Art. 12 (27 pages).
-
(2007)
ACM Trans. Design Autom. Electron. Syst.
, vol.12
, pp. 12
-
-
Chang, H.1
Sapatnekar, S.S.2
-
36
-
-
27944447029
-
Gate sizing using a statistical delay model
-
E. Jacobs and M. Berkelaar, "Gate sizing using a statistical delay model," in Proc. Design, Autom., Test in Eur., 2000, pp. 283-290.
-
(2000)
Proc. Design, Autom., Test in Eur.
, pp. 283-290
-
-
Jacobs, E.1
Berkelaar, M.2
-
37
-
-
4444264520
-
Novel sizing algorithm for yield improvement under process variation in nanometer technology
-
Jun.
-
S. H. Choi, B. C. Paul, and K. Roy, "Novel sizing algorithm for yield improvement under process variation in nanometer technology," in Proc. ACM/IEEE Design Autom. Conf., Jun. 2004, pp. 454-459.
-
(2004)
Proc. ACM/ IEEE Design Autom. Conf.
, pp. 454-459
-
-
Choi, S.H.1
Paul, B.C.2
Roy, K.3
-
38
-
-
33751394193
-
Statistical gate sizing for timing yield optimization
-
Nov.
-
D. Sinha, N. V. Shenoy, and H. Zhou, "Statistical gate sizing for timing yield optimization," in Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design, Nov. 2005, pp. 1037-1042.
-
(2005)
Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design
, pp. 1037-1042
-
-
Sinha, D.1
Shenoy, N.V.2
Zhou, H.3
-
39
-
-
27944476890
-
Circuit optimization using statistical static timing analysis
-
Jun.
-
A. Agarwal, K. Chopra, D. Blaauw, and V. Zolotov, "Circuit optimization using statistical static timing analysis," in Proc. ACM/IEEE Design Autom. Conf., Jun. 2005, pp. 338-342.
-
(2005)
Proc. ACM/ IEEE Design Autom. Conf.
, pp. 338-342
-
-
Agarwal, A.1
Chopra, K.2
Blaauw, D.3
Zolotov, V.4
-
40
-
-
33751414776
-
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation
-
Nov.
-
K. Chopra, S. Shah, A. Srivastava, D. Blaauw, and D. Sylvester, "Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation," in Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design, Nov. 2005, pp. 1023-1028.
-
(2005)
Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design
, pp. 1023-1028
-
-
Chopra, K.1
Shah, S.2
Srivastava, A.3
Blaauw, D.4
Sylvester, D.5
-
41
-
-
4444333242
-
A methodology to improve timing yield in the presence of process variations
-
Jun.
-
S. Raj, S. B. K. Vrudhala, and J. Wang, "A methodology to improve timing yield in the presence of process variations," in Proc. ACM/IEEE Design Autom. Conf., Jun. 2004, pp. 448-453.
-
(2004)
Proc. ACM/IEEE Design Autom. Conf.
, pp. 448-453
-
-
Raj, S.1
Vrudhala, S.B.K.2
Wang, J.3
-
42
-
-
27944441297
-
An efficient algorithm for statistical minimization of total power under timing yield constraints
-
19.1, Proceedings 2005, 42nd Design Automation Conference, DAC 2005
-
M. Mani, A. Devgan, and M. Orshansky, "An efficient algorithm for statistical power under timing yield constraints," in Proc. ACM/IEEE Design Autom. Conf., Jun. 2005, pp. 309-314. (Pubitemid 41675451)
-
(2005)
Proceedings - Design Automation Conference
, pp. 309-314
-
-
Mani, M.1
Devgan, A.2
Orshansky, M.3
-
43
-
-
34547142836
-
Variability driven gate sizing for binning yield optimization
-
DOI 10.1145/1146909.1147152, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06
-
A. Davoodi and A. Srivastava, "Variability driven gate sizing for binning yield optimization," in Proc. ACM/IEEE Design Autom. Conf., 2006, pp. 959-964. (Pubitemid 47114034)
-
(2006)
Proceedings - Design Automation Conference
, pp. 959-964
-
-
Davoodi, A.1
Srivastava, A.2
-
44
-
-
27944492787
-
Robust gate sizing by geometric programming
-
19.2, Proceedings 2005, 42nd Design Automation Conference, DAC 2005
-
J. Singh, V. Nookala, T. Luo, and S. Sapatnekar, "Robust gate sizing by geometric programming," in Proc. ACM/IEEE Design Autom. Conf., Jun. 2005, pp. 315-320. (Pubitemid 41675452)
-
(2005)
Proceedings - Design Automation Conference
, pp. 315-320
-
-
Singh, J.1
Nookala, V.2
Luo, Z.-Q.3
Sapatnekar, S.4
-
45
-
-
33751398442
-
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations
-
Nov.
-
X. Li, J. Le, M. Celik, and L. T. Pileggi, "Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations," in Proc. IEEE/ACM Int. Conf. on Comput.- Aided Design, Nov. 2005, pp. 844-851.
-
(2005)
Proc. IEEE/ACM Int. Conf. on Comput.- Aided Design
, pp. 844-851
-
-
Li, X.1
Le, J.2
Celik, M.3
Pileggi, L.T.4
-
46
-
-
34547188326
-
Criticality computation in parameterized statistical timing
-
DOI 10.1145/1146909.1146929, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06
-
J. Xiong, V. Zolotov, N. Venkateswaran, and C. Visweswariah, "Criticality computation in parameterized statistical timing," in Proc. ACM/ IEEE Design Autom. Conf., Jul. 2006, pp. 63-68. (Pubitemid 47113868)
-
(2006)
Proceedings - Design Automation Conference
, pp. 63-68
-
-
Xiong, J.1
Zolotov, V.2
Venkateswaran, N.3
Visweswariah, C.4
-
47
-
-
50249177742
-
Clustering based pruning for statistical criticality computation under process variations
-
Nov.
-
H. Mogal, H. Qian, S. S. Sapatnekar, and K. Bazargan, "Clustering based pruning for statistical criticality computation under process variations," in Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design, Nov. 2007, pp. 340-343.
-
(2007)
Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design
, pp. 340-343
-
-
Mogal, H.1
Qian, H.2
Sapatnekar, S.S.3
Bazargan, K.4
-
48
-
-
34347239371
-
Refined statistical static timing analysis through learning spatial delay correlations
-
DOI 10.1145/1146909.1146952, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06
-
B. Lee, L. Wang, and M. S. Abadir, "Refined statistical static timing analysis through learning spatial delay correlations," in Proc. ACM/ IEEE Design Autom. Conf., July 2006, pp. 149-154. (Pubitemid 47129490)
-
(2006)
Proceedings - Design Automation Conference
, pp. 149-154
-
-
Lee, B.N.1
Wang, L.-C.2
Abadir, M.S.3
-
49
-
-
34547355933
-
Design-silicon timing correlation- A data mining perspective
-
June
-
L. Wang, P. Bastani, and M. S. Abadir, "Design-silicon timing correlation- a data mining perspective," in Proc. ACM/IEEE Design Autom. Conf., June 2007, pp. 385-389.
-
(2007)
Proc. ACM/ IEEE Design Autom. Conf.
, pp. 385-389
-
-
Wang, L.1
Bastani, P.2
Abadir, M.S.3
-
50
-
-
34547142836
-
Variability driven gate sizing for binning yield optimization
-
Jul.
-
A. Davoodi and A. Srivastava, "Variability driven gate sizing for binning yield optimization," in Proc. ACM/IEEE Design Autom. Conf., Jul. 2006, pp. 956-964.
-
(2006)
Proc. ACM/ IEEE Design Autom. Conf.
, pp. 956-964
-
-
Davoodi, A.1
Srivastava, A.2
-
51
-
-
34547229372
-
A reconfigurable design-for-debug infrastructure for SoCs
-
DOI 10.1145/1146909.1146916, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06
-
M. Abramovici, P. Bradley, K. Dwarakanath, P. Levin, G. Memmi, and D. Miller, "A reconfigurable design-for-debug infrastructure for SoCs," in Proc. ACM/IEEE Design Autom. Conf., Jul. 2006, pp. 7-12. (Pubitemid 47113859)
-
(2006)
Proceedings - Design Automation Conference
, pp. 7-12
-
-
Abramovici, M.1
Bradley, P.2
Dwarakanath, K.3
Levin, P.4
Memmi, G.5
Miller, D.6
-
52
-
-
34547322816
-
Confidence scalable post-silicon statistical delay prediction under process variations
-
DOI 10.1109/DAC.2007.375216, 4261235, 2007 44th ACM/IEEE Design Automation Conference, DAC'07
-
Q. Liu and S. S. Sapatnekar, "Confidence scalable post-silicon statistical delay prediction under process variations," in Proc. ACM/IEEE Design Autom. Conf., Jun. 2007, pp. 497-502. (Pubitemid 47130017)
-
(2007)
Proceedings - Design Automation Conference
, pp. 497-502
-
-
Qunzeng, L.1
Sapatnekar, S.S.2
-
53
-
-
70349089251
-
Synthesizing a representative critical path for post-silicon delay prediction
-
Apr.
-
Q. Liu and S. S. Sapatnekar, "Synthesizing a representative critical path for post-silicon delay prediction," in Proc. ACMInt. Symp. on Physical Design, Apr. 2009, pp. 183-190.
-
(2009)
Proc. ACMInt. Symp. on Physical Design
, pp. 183-190
-
-
Liu, Q.1
Sapatnekar, S.S.2
-
54
-
-
0036539969
-
A Monte Carlo approach for maximum power estimation based on extreme value theory
-
DOI 10.1109/43.992765, PII S0278007002024740
-
N. E. Evmorfopoulos, G. I. Stamoulis, and J. N. Avaritsiotis, "A Monte Carlo approach for maximum power estimation based on extreme value theory," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, pp. 415-432, Apr. 2002. (Pubitemid 34474856)
-
(2002)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.21
, Issue.4
, pp. 415-432
-
-
Evmorfopoulos, N.E.1
Stamoulis, G.I.2
Avaritsiotis, J.N.3
-
55
-
-
79957844922
-
-
Semiconductor Industry Association International Technology Roadmap for Semiconductors
-
Semiconductor Industry Association, International Technology Roadmap for Semiconductors 1997-2005.
-
(1997)
-
-
-
56
-
-
0036474411
-
Hierarchical analysis of power distribution networks
-
DOI 10.1109/43.980256, PII S0278007002010552
-
M. Zhao, R. V. Panda, S. S. Sapatnekar, and D. Blaauw, "Hierarchical analysis of power distribution networks," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, pp. 159-168, Feb. 2002. (Pubitemid 34266011)
-
(2002)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.21
, Issue.2
, pp. 159-168
-
-
Zhao, M.1
Panda, R.V.2
Sapatnekar, S.S.3
Blaauw, D.4
-
57
-
-
0036811946
-
A multigrid-like technique for power grid analysis
-
DOI 10.1109/TCAD.2002.802271
-
J. Kozhaya, S. R. Nassif, and F. N. Najm, "A multigrid-like technique for power grid analysis," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, pp. 1148-1160, Oct. 2002. (Pubitemid 35369838)
-
(2002)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.21
, Issue.10
, pp. 1148-1160
-
-
Kozhaya, J.N.1
Nassif, S.R.2
Najm, F.N.3
-
58
-
-
0043092199
-
Power grid reduction based on algebraic multigrid principles
-
H. Su, E. Acar, and S. R. Nassif, "Power grid reduction based on algebraic multigrid principles," in Proc. ACM/IEEE Design Autom. Conf., 2003, pp. 109-112.
-
(2003)
Proc. ACM/ IEEE Design Autom. Conf.
, pp. 109-112
-
-
Su, H.1
Acar, E.2
Nassif, S.R.3
-
59
-
-
15244343665
-
On-chip power-supply network optimization using multigrid-based technique
-
DOI 10.1109/TCAD.2004.842802
-
K. Wang and M. Marek-Sadowska, "On-chip power-supply network optimization using multigrid-based technique," IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 24, pp. 407-417, Mar. 2005. (Pubitemid 40384633)
-
(2005)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.24
, Issue.3
, pp. 407-417
-
-
Wang, K.1
Marek-Sadowska, M.2
-
60
-
-
79957849382
-
-
A multigrid tutorial," [Online]. Available:
-
W. L. Briggs, "A multigrid tutorial," [Online]. Available: http://www. llnl.gov/CASC/people/henson/mgtut/ps/mgtut.pdf
-
-
-
Briggs, W.L.1
-
62
-
-
0041589396
-
Random walks in a supply network
-
H. Qian, S. R. Nassif, and S. S. Sapatnekar, "Random walks in a supply network," in Proc. ACM/IEEE Design Autom. Conf., 2003, pp. 93-98.
-
(2003)
Proc. ACM/IEEE Design Autom. Conf.
, pp. 93-98
-
-
Qian, H.1
Nassif, S.R.2
Sapatnekar, S.S.3
-
63
-
-
23744444927
-
Power grid analysis using random walks
-
DOI 10.1109/TCAD.2005.850863
-
H. Qian, S. R. Nassif, and S. S. Sapatnekar, "Power grid analysis using random walks," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, pp. 1204-1224, Aug. 2005. (Pubitemid 41118742)
-
(2005)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.24
, Issue.8
, pp. 1204-1224
-
-
Qian, H.1
Nassif, S.R.2
Sapatnekar, S.S.3
-
66
-
-
31344469363
-
Optimal placement of power-supply pads and pins
-
DOI 10.1109/TCAD.2005.852459
-
M. Zhao, Y. Fu, V. Zolotov, S. Sundareswaran, and R. Panda, "Optimal placement of power-supply pads and pins," IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 25, pp. 144-154, Jan. 2006. (Pubitemid 43146105)
-
(2006)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.25
, Issue.1
, pp. 144-154
-
-
Zhao, M.1
Fu, Y.2
Zolotov, V.3
Sundareswaran, S.4
Panda, R.5
-
67
-
-
51449097297
-
Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion
-
T. Sato, H. Onodera, and M. Hashimoto, "Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion," in Proc. Asia/South Pacific Design Autom. Conf., 2005, pp. 723-728.
-
(2005)
Proc. Asia/South Pacific Design Autom. Conf.
, pp. 723-728
-
-
Sato, T.1
Onodera, H.2
Hashimoto, M.3
-
68
-
-
18744408849
-
Congestion-aware topology optimization of structured power/ground networks
-
DOI 10.1109/TCAD.2005.846369, The International Symposium on Physical Design 2004
-
J. Singh and S. S. Sapatnekar, "Congestion-aware topology optimization of structured power/ground networks," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, pp. 683-695, May 2005. (Pubitemid 40665622)
-
(2005)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.24
, Issue.5
, pp. 683-695
-
-
Singh, J.1
Sapatnekar, S.S.2
-
70
-
-
0036058076
-
Congestion-driven codesign of power and signal networks
-
H. Su, J. Hu, S. R. Nassif, and S. S. Sapatnekar, "Congestion-driven codesign of power and signal networks," in Proc. ACM/IEEE Design Autom. Conf., 2002, pp. 477-480.
-
(2002)
Proc. ACM/ IEEE Design Autom. Conf.
, pp. 477-480
-
-
Su, H.1
Hu, J.2
Nassif, S.R.3
Sapatnekar, S.S.4
-
71
-
-
10044229223
-
A methodology for the simultaneous design of supply and signal networks
-
Dec.
-
H. Su, J. Hu, S. S. Sapatnekar, and S. R. Nassif, "A methodology for the simultaneous design of supply and signal networks," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, pp. 1614-1624, Dec. 2004.
-
(2004)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.23
, pp. 1614-1624
-
-
Su, H.1
Hu, J.2
Sapatnekar, S.S.3
Nassif, S.R.4
-
72
-
-
0344089095
-
Optimal decoupling capacitor sizing and placement for standard cell layout designs
-
Apr.
-
H. Su, S. S. Sapatnekar, and S. R. Nassif, "Optimal decoupling capacitor sizing and placement for standard cell layout designs," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, pp. 428-436, Apr. 2003.
-
(2003)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.22
, pp. 428-436
-
-
Su, H.1
Sapatnekar, S.S.2
Nassif, S.R.3
-
73
-
-
64549114103
-
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
-
P. Zhou, K. Sridharan, and S. S. Sapatnekar, "Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors," in Proc. Asia/South Pacific Design Autom. Conf., 2010, pp. 179-184.
-
(2010)
Proc. Asia/South Pacific Design Autom. Conf.
, pp. 179-184
-
-
Zhou, P.1
Sridharan, K.2
Sapatnekar, S.S.3
-
74
-
-
58849113571
-
Design and implementation of active decoupling capacitor circuits for power supply regulation in digital ics
-
Feb.
-
J. Gu, R. Harjani, and C. Kim, "Design and implementation of active decoupling capacitor circuits for power supply regulation in digital ics," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 2, pp. 292-301, Feb. 2009.
-
(2009)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
, vol.17
, Issue.2
, pp. 292-301
-
-
Gu, J.1
Harjani, R.2
Kim, C.3
-
75
-
-
33845692228
-
Heat generation and transport in nanometer-scale transistors
-
DOI 10.1109/JPROC.2006.879794
-
E. Pop, S. Sinha, and K. E. Goodson, "Heat generation and transport in nanometer-scale transistors," Proc. IEEE, vol. 94, pp. 1587-1601, Aug. 2006. (Pubitemid 46432337)
-
(2006)
Proceedings of the IEEE
, vol.94
, Issue.8
, pp. 1587-1601
-
-
Pop, E.1
Sinha, S.2
Goodson, K.E.3
-
77
-
-
34548279935
-
High-efficiency green function-based thermal simulation algorithms
-
DOI 10.1109/TCAD.2007.895754
-
Y. Zhan and S. S. Sapatnekar, "High efficiency Green function-based thermal simulation algorithms," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, pp. 1661-1675, Sep. 2007. (Pubitemid 47330108)
-
(2007)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.26
, Issue.9
, pp. 1661-1675
-
-
Zhan, Y.1
Sapatnekar, S.S.2
-
78
-
-
33846609148
-
Accelerated chip-level thermal analysis using multilayer Green's function
-
Feb.
-
B. Wang and P. Mazumder, "Accelerated chip-level thermal analysis using multilayer Green's function," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, pp. 325-344, Feb. 2007.
-
(2007)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.26
, pp. 325-344
-
-
Wang, B.1
Mazumder, P.2
-
82
-
-
28444445319
-
Joint exploration of architectural and physical design spaces with thermal consideration
-
ISLPED'05 - Proceedings of the 2005 International Symposium on Low Power Electronics and Design
-
Y. W. Wu, C.-L. Yang, P.-H. Yuh, and Y.-W. Chang, "Joint exploration of architectural and physical design spaces with thermal consideration," in Proc. Int. Symp. of Low Power Electronic Devices, 2005, pp. 123-126. (Pubitemid 41731640)
-
(2005)
Proceedings of the International Symposium on Low Power Electronics and Design
, pp. 123-126
-
-
Wu, Y.-W.1
Yang, C.-L.2
Yuh, P.-H.3
Chang, Y.-W.4
-
83
-
-
27444438269
-
A case for thermal-aware floorplanning at the microarchitectural level
-
Sep.
-
K. Sankaranarayanan, S. Velusamy, M. Stan, and K. Skadron, "A case for thermal-aware floorplanning at the microarchitectural level," J. Instruction- Level Parallelism, vol. 8, Sep. 2005.
-
(2005)
J. Instruction- Level Parallelism
, vol.8
-
-
Sankaranarayanan, K.1
Velusamy, S.2
Stan, M.3
Skadron, K.4
-
84
-
-
34047186502
-
Microarchitectural floorplanning under performance and thermal tradeoff
-
M. Healy,M.Vittes, M. Ekpanyapong, C. Ballapuram, S. K. Lim, H.-H. S. Lee, and G. H. Loh, "Microarchitectural floorplanning under performance and thermal tradeoff," in Proc. Design, Autom., and Test in Eur., 2006, pp. 1-6.
-
(2006)
Proc. Design, Autom., and Test in Eur.
, pp. 1-6
-
-
Healy, M.1
Vittes, M.2
Ekpanyapong, M.3
Ballapuram, C.4
Lim, S.K.5
Lee, H.-H.S.6
Loh, G.H.7
-
85
-
-
34247252970
-
Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis
-
DOI 10.1145/1165573.1165644, ISLPED'06 - Proceedings of the 2006 International Symposium on Low Power Electronics and Design
-
V. Nookala, D. J. Lilja, and S. S. Sapatnekar, "Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis," in Proc. Int. Symp. of Low Power Electronic Devices, 2006, pp. 298-303. (Pubitemid 46609753)
-
(2006)
Proceedings of the International Symposium on Low Power Electronics and Design
, vol.2006
, pp. 298-303
-
-
Nookala, V.1
Lilja, D.J.2
Sapatnekar, S.S.3
-
86
-
-
16244385917
-
A thermal-driven floorplanning algorithm for 3D ICs
-
4C.3, ICCAD-2004 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
-
J. Cong, J. Wei, and Y. Zhang, "A thermal-driven floorplanning algorithm for 3D ICs," in Proc. ACM Int. Symp. on Physical Design, 2004, pp. 306-313. (Pubitemid 40449251)
-
(2004)
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
, pp. 306-313
-
-
Cong, J.1
Wei, J.2
Zhang, Y.3
-
87
-
-
34047110813
-
3D floorplanning with thermal vias
-
E.Wong and S. K. Lim, "3D floorplanning with thermal vias," in Proc. Design, Autom., Test in Eur., 2006, pp. 878-883.
-
(2006)
Proc. Design, Autom., Test in Eur.
, pp. 878-883
-
-
Wong, E.1
Lim, S.K.2
-
88
-
-
50249153041
-
3D-STAF: Scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits
-
P. Zhou, Y. Ma, Z. Li, R. P. Dick, L. Shang, H. Zhou, X. Hong, and Q. Zhou, "3D-STAF: Scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits," in Proc. IEEE/ACMInt. Conf. on Comput.-Aided Design, 2007, pp. 590-597.
-
(2007)
Proc. IEEE/ACMInt. Conf. on Comput.-Aided Design
, pp. 590-597
-
-
Zhou, P.1
Ma, Y.2
Li, Z.3
Dick, R.P.4
Shang, L.5
Zhou, H.6
Hong, X.7
Zhou, Q.8
-
89
-
-
0033871060
-
Cell-level placement for improving substrate thermal distribution
-
Feburary
-
C. H. Tsai and S. M. Kang, "Cell-level placement for improving substrate thermal distribution," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, pp. 253-266, Feburary 2000.
-
(2000)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.19
, pp. 253-266
-
-
Tsai, C.H.1
Kang, S.M.2
-
91
-
-
0347409236
-
Efficient thermal placement of standard cells in 3D ICs using a force directed approach
-
Nov.
-
B. Goplen and S. S. Sapatnekar, "Efficient thermal placement of standard cells in 3D ICs using a force directed approach," in Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design, Nov. 2003, pp. 86-89.
-
(2003)
Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design
, pp. 86-89
-
-
Goplen, B.1
Sapatnekar, S.S.2
-
92
-
-
34547301387
-
Placement of 3D ICs with thermal and interlayer via considerations
-
DOI 10.1109/DAC.2007.375239, 4261258, 2007 44th ACM/IEEE Design Automation Conference, DAC'07
-
B. Goplen and S. S. Sapatnekar, "Placement of 3D ICs with thermal and interlayer via considerations," in Proc. ACM/IEEE Design Autom. Conf., 2007, pp. 626-631. (Pubitemid 47130040)
-
(2007)
Proceedings - Design Automation Conference
, pp. 626-631
-
-
Goplen, B.1
Sapatnekar, S.2
-
93
-
-
46649110782
-
Thermal-aware 3D IC placement via transformation
-
J. Cong, G. Luo, J. Wei, and Y. Zhang, "Thermal-aware 3D IC placement via transformation," in Proc. Asia/South Pacific Design Autom. Conf., 2007, pp. 780-785.
-
(2007)
Proc. Asia/South Pacific Design Autom. Conf.
, pp. 780-785
-
-
Cong, J.1
Luo, G.2
Wei, J.3
Zhang, Y.4
-
96
-
-
33748589691
-
Temperature-aware routing in 3D ICs
-
1594700, Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
-
T. Zhang, Y. Zhan, and S. S. Sapatnekar, "Temperature-aware routing in 3D ICs," in Proc. Asia/South Pacific Design Autom. Conf., 2006, pp. 309-314. (Pubitemid 44375945)
-
(2006)
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
, vol.2006
, pp. 309-314
-
-
Zhang, T.1
Zhan, Y.2
Sapatnekar, S.S.3
-
97
-
-
22544455956
-
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems
-
DOI 10.1109/TCAD.2005.850895
-
L. Yan, J. Luo, and N. K. Jha, "Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, pp. 1030-1041, July 2005. (Pubitemid 41013052)
-
(2005)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
, vol.24
, Issue.7
, pp. 1030-1041
-
-
Yan, L.1
Luo, J.2
Jha, N.K.3
-
98
-
-
0346148512
-
Combined dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems
-
L. Yan, J. Luo, and N. K. Jha, "Combined dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems," in Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design, 2003, pp. 30-37.
-
(2003)
Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design
, pp. 30-37
-
-
Yan, L.1
Luo, J.2
Jha, N.K.3
-
99
-
-
0036917242
-
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
-
S. M. Martin, K. Flautner, T. Mudge, and D. Blaauw, "Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads," in Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design, 2002, pp. 721-725.
-
(2002)
Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design
, pp. 721-725
-
-
Martin, S.M.1
Flautner, K.2
Mudge, T.3
Blaauw, D.4
-
100
-
-
21744455802
-
Energy-aware supply and body biasing voltage scheduling algorithm
-
S. Yajuan, W. Zuodong, and W. Shaojun, "Energy-aware supply and body biasing voltage scheduling algorithm," in Proc. Int. Conf. on Solid State and Integrated Circuits Technology, 2004, pp. 1956-1959.
-
(2004)
Proc. Int. Conf. on Solid State and Integrated Circuits Technology
, pp. 1956-1959
-
-
Yajuan, S.1
Zuodong, W.2
Shaojun, W.3
-
101
-
-
3042565410
-
Overhead- conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems
-
A. Andrei, M. Schmitz, P. Eles, Z. Peng, and B. M. Al-Hashimi, "Overhead- conscious voltage selection for dynamic and leakage energy reduction of time-constrained systems," in Proc. Design, Automation, and Test in Europe, 2004, pp. 518-523.
-
(2004)
Proc. Design, Automation, and Test in Europe
, pp. 518-523
-
-
Andrei, A.1
Schmitz, M.2
Eles, P.3
Peng, Z.4
Al-Hashimi, B.M.5
-
102
-
-
28144453785
-
A 90 nm variable-frequency clock system for a power-managed Itanium-family processor
-
T. Fischer, F. Anderson, B. Patella, and S. Naffziger, "A 90 nm variable-frequency clock system for a power-managed Itanium-family processor," in Proc. IEEE Int. Solid-State Circuits Conf., 2005, pp. 294-299, 599.
-
(2005)
Proc. IEEE Int. Solid-State Circuits Conf.
, vol.599
, pp. 294-299
-
-
Fischer, T.1
Anderson, F.2
Patella, B.3
Naffziger, S.4
-
103
-
-
28144465061
-
Power and temperature control on a 90nm itanium®-family processor
-
16.7, 2005 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
-
C. Piorier, R.McGowen, C. Bostak, and S. Naffziger, "Power and temperature control on an Itanium-family processor," in Proc. IEEE Int. Solid-State Circuits Conf., 2005, pp. 304-305. (Pubitemid 41696575)
-
(2005)
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
, vol.48
, pp. 304-305
-
-
Poirier, C.1
McGowen, R.2
Bostak, C.3
Naffzigera, S.4
-
104
-
-
31344454872
-
Power and temperature control on a 90-nm Itanium family processor
-
DOI 10.1109/JSSC.2005.859902
-
R. McGowen, C. A. Poirier, C. Bostak, J. Ignowski, M. Millican, W. H. Parks, and S. Naffziger, "Power and temperature control on a 90-nm Itanium family processor," IEEE J. Solid-State Circuits, vol. 41, pp. 229-237, Jan. 2006. (Pubitemid 43145980)
-
(2006)
IEEE Journal of Solid-State Circuits
, vol.41
, Issue.1
, pp. 229-237
-
-
McGowen, R.1
Poirier, C.A.2
Bostak, C.3
Ignowski, J.4
Millican, M.5
Parks, W.H.6
Naffziger, S.7
-
106
-
-
1542690244
-
Soft errors in advanced semiconductor devices-part i: The three radiation sources
-
PII S1530438801040744
-
R. C. Baumann, "Soft errors in advanced semiconductor devices-Part i: The three radiation sources," IEEE Trans. Devices Mater. Rel., vol. 1, pp. 17-22, Mar. 2001. (Pubitemid 33778193)
-
(2001)
IEEE Transactions on Device and Materials Reliability
, vol.1
, Issue.1
, pp. 17-22
-
-
Baumann, R.C.1
-
107
-
-
9144234352
-
Characterization of soft errors caused by single event upsets in CMOS processes
-
Apr.-Jun.
-
T. Karnik, P. Hazucha, and J. Patel, "Characterization of soft errors caused by single event upsets in CMOS processes," IEEE Trans. Dependable and Secure Computing, vol. 1, pp. 128-143, Apr.-Jun. 2004.
-
(2004)
IEEE Trans. Dependable and Secure Computing
, vol.1
, pp. 128-143
-
-
Karnik, T.1
Hazucha, P.2
Patel, J.3
-
108
-
-
46149126905
-
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques
-
M. Choudhury, Q. Zhou, and K. Mohanram, "Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques," in Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design, 2006, pp. 204-209.
-
(2006)
Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design
, pp. 204-209
-
-
Choudhury, M.1
Zhou, Q.2
Mohanram, K.3
-
109
-
-
77957911501
-
LEAP: Layout design through error-aware placement for soft-error resilient sequential cell design
-
H. Lee, K. Lilja, M. Bounasser, P. Relangi, I. Linscott, U. Inan, and S. Mitra, "LEAP: Layout design through error-aware placement for soft-error resilient sequential cell design," in Proc. IEEE Int. Rel.Phys. Symp., 2010, pp. 203-212.
-
(2010)
Proc. IEEE Int. Rel.Phys. Symp.
, pp. 203-212
-
-
Lee, H.1
Lilja, K.2
Bounasser, M.3
Relangi, P.4
Linscott, I.5
Inan, U.6
Mitra, S.7
-
110
-
-
84949193854
-
Impact of negative bias temperature instability on digital circuit reliability
-
V. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishnan, "Impact of negative bias temperature instability on digital circuit reliability," in Proc. IEEE Int. Rel.Phys. Symp., 2002, pp. 248-253.
-
(2002)
Proc. IEEE Int. Rel.Phys. Symp.
, pp. 248-253
-
-
Reddy, V.1
Krishnan, A.T.2
Marshall, A.3
Rodriguez, J.4
Natarajan, S.5
Rost, T.6
Krishnan, S.7
-
111
-
-
0842288263
-
NBTI impact on transistor and circuit: Models, mechanisms and scaling effects
-
A. T. Krishnan, V. Reddy, S. Chakravarthi, J. Rodriguez, S. John, and S. Krishnan, "NBTI impact on transistor and circuit: Models, mechanisms and scaling effects," in Proc. IEEE Int. Electronic Devices Meeting, 2003, pp. 145.1-14.5.4.
-
(2003)
Proc. IEEE Int. Electronic Devices Meeting
, pp. 1451-1454
-
-
Krishnan, A.T.1
Reddy, V.2
Chakravarthi, S.3
Rodriguez, J.4
John, S.5
Krishnan, S.6
-
112
-
-
79957840501
-
-
Negative bias temperature instability: physics materials process and circuit issues[Online]. Available
-
D. K. Schroder, Negative bias temperature instability: physics, materials, process, and circuit issues 2005 [Online]. Available: http://www. ewh.ieee.org/r5/denver/sscs/Presentations/2005.08.Schroder.pdf
-
(2005)
-
-
Schroder, D.K.1
-
113
-
-
10044241027
-
A critical examination of the mechanics of dynamic NBTI for pMOSFETs
-
M. A. Alam, "A critical examination of the mechanics of dynamic NBTI for pMOSFETs," in Proc. IEEE Int. Electron Devices Meeting, 2003, pp. 14.4.1-14.4.4.
-
(2003)
Proc. IEEE Int. Electron Devices Meeting
, pp. 1441-1444
-
-
Alam, M.A.1
-
114
-
-
76349111305
-
A comprehensive framework for predictive modeling of negative bias temperature instability
-
S. Chakravarthi, A. T. Krishnan, V. Reddy, C. Machala, and S. Krishnan, "A comprehensive framework for predictive modeling of negative bias temperature instability," in Proc. IEEE Int. Rel. Phys. Symp., 2004, pp. 273-282.
-
(2004)
Proc. IEEE Int. Rel. Phys. Symp.
, pp. 273-282
-
-
Chakravarthi, S.1
Krishnan, A.T.2
Reddy, V.3
Machala, C.4
Krishnan, S.5
-
115
-
-
21644482021
-
NBTI: What we know and what we need to know - A tutorial addressing the current understanding and challenges for the future
-
2004 IEEE International Integrated Reliability Workshop Final Report
-
J. G. Massey, "NBTI: What we know and what we need to know-A tutorial addressing the current understanding and challenges for the future," in Proc. IEEE Int. Integr. Rel. Workshop Final Rep., 2004, pp. 199-211. (Pubitemid 40930066)
-
(2004)
IEEE International Integrated Reliability Workshop Final Report
, pp. 199-211
-
-
Massey, J.G.1
-
116
-
-
0036081925
-
Impact of negative bias temperature instability on digital circuit reliability
-
V. Reddy, A. T. Krishnan, A. Marshall, J. Rodriguez, S. Natarajan, T. Rost, and S. Krishnan, "Impact of negative bias temperature instability on digital circuit reliability," in Proc. IEEE Int. Rel. Phys. Symp., Apr. 2002, pp. 248-254. (Pubitemid 34668952)
-
(2002)
Annual Proceedings - Reliability Physics (Symposium)
, pp. 248-254
-
-
Reddy, V.1
Krishnan, A.T.2
Marshall, A.3
Rodriguez, J.4
Natarajan, S.5
Rost, T.6
Krishnan, S.7
-
117
-
-
46149102717
-
An analytical model for negative bias temperature instability (NBTI)
-
S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, "An analytical model for negative bias temperature instability (NBTI)," in Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design, 2006, pp. 493-496.
-
(2006)
Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design
, pp. 493-496
-
-
Kumar, S.V.1
Kim, C.H.2
Sapatnekar, S.S.3
-
118
-
-
34547358150
-
NBTI-aware synthesis of digital circuits
-
DOI 10.1109/DAC.2007.375189, 4261208, 2007 44th ACM/IEEE Design Automation Conference, DAC'07
-
S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, "NBTI-aware synthesis of digital circuits," in Proc. ACM/IEEE Design Autom. Conf., 2007, pp. 370-375. (Pubitemid 47129990)
-
(2007)
Proceedings - Design Automation Conference
, pp. 370-375
-
-
Kumar, S.V.1
Kim, C.H.2
Sapatnekar, S.S.3
-
119
-
-
79953092815
-
Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits
-
[Online]. Available:
-
S. V.Kumar, C.H. Kim, and S. S. Sapatnekar, "Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. [Online]. Available: http://ieeexplore.ieee.org/xpls/abs-all.jsp?arnumber=5371864&tag=1
-
IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
-
-
Kumar, S.V.1
Kim, C.H.2
Sapatnekar, S.S.3
-
120
-
-
41549122836
-
Silicon odometer: An on-chip reliability monitor for measuring frequency degradation of digital circuits
-
DOI 10.1109/JSSC.2008.917502
-
T.-H. Kim, R. Persaud, and C. H. Kim, "Silicon odometer: An on-chip reliability monitor for measuring frequency degradation of digital circuits," IEEE J. Solid-State Circuits, vol. 43, pp. 874-880, Apr. 2008. (Pubitemid 351464080)
-
(2008)
IEEE Journal of Solid-State Circuits
, vol.43
, Issue.4
, pp. 874-880
-
-
Kim, T.-H.1
Persaud, R.2
Kim, C.H.3
-
121
-
-
0036508455
-
Reliability limits for the gate insulator in CMOS technology
-
J. H. Stathis, "Reliability limits for the gate insulator in CMOS technology," IBM J. Res. Develop., vol. 46, pp. 265-286, Mar./May 2002. (Pubitemid 34692351)
-
(2002)
IBM Journal of Research and Development
, vol.46
, Issue.2-3
, pp. 265-286
-
-
Stathis, J.H.1
-
122
-
-
0036508417
-
CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics
-
E. Y. Wu, E. J. Nowak, A. Vayshenker, W. L. Lai, and D. L. Harmon, "CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics," IBM J. Res. Develop., vol. 46, pp. 287-298, Mar./May 2002. (Pubitemid 34692352)
-
(2002)
IBM Journal of Research and Development
, vol.46
, Issue.2-3
, pp. 287-298
-
-
Wu, E.Y.1
Nowak, E.J.2
Vayshenker, A.3
Lai, W.L.4
Harmon, D.L.5
-
123
-
-
0038529280
-
Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits
-
PII S1530438801042524
-
J. H. Stathis, "Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits," IEEE Trans. Devices Mater. Rel., vol. 1, pp. 43-59, Mar. 2001. (Pubitemid 33778196)
-
(2001)
IEEE Transactions on Device and Materials Reliability
, vol.1
, Issue.1
, pp. 43-59
-
-
Stathis, J.H.1
-
124
-
-
34250742624
-
Prediction of logic product failure due to thin-gate oxide breakdown
-
DOI 10.1109/RELPHY.2006.251187, 4017128, 2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual
-
Y. H. Lee, N. Mielke, M. Agostinelli, S. Gupta, R. Lu, and W. McMahon, "Prediction of logic product failure due to thin-gate oxide breakdown," in Proc. IEEE Int. Rel. Phys. Symp., Mar. 2006, pp. 18-28. (Pubitemid 46964486)
-
(2006)
IEEE International Reliability Physics Symposium Proceedings
, pp. 18-28
-
-
Lee, Y.-H.1
Mielke, N.2
Agostinelli, M.3
Gupta, S.4
Lu, R.5
McMahon, W.6
-
125
-
-
57849125876
-
A statistical approach for full-chip gate-oxide reliability analysis
-
Nov.
-
K. Chopra, C. Zhuo, D. Blaauw, and D. Sylvester, "A statistical approach for full-chip gate-oxide reliability analysis," in Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design, Nov. 2008, pp. 698-705.
-
(2008)
Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design
, pp. 698-705
-
-
Chopra, K.1
Zhuo, C.2
Blaauw, D.3
Sylvester, D.4
-
127
-
-
77951019768
-
Reliable cache design with detection of gate oxide breakdown using BIST
-
F. Ahmed and L. Milor, "Reliable cache design with detection of gate oxide breakdown using BIST," in Proc. IEEE Int. Conf. on Comput. Design, 2009, pp. 366-371.
-
(2009)
Proc. IEEE Int. Conf. on Comput. Design
, pp. 366-371
-
-
Ahmed, F.1
Milor, L.2
-
128
-
-
0001310648
-
Reliability effects on MOS transistors due to hot-carrier injection
-
Feb.
-
K. Chen, S. Saller, I. Groves, and D. Scott, "Reliability effects on MOS transistors due to hot-carrier injection," IEEE Trans. Electron Devices, vol. 32, pp. 386-393, Feb. 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.32
, pp. 386-393
-
-
Chen, K.1
Saller, S.2
Groves, I.3
Scott, D.4
-
129
-
-
77950291757
-
-
Ph.D. dissertation, Purdue Univ., West Lafayette, IN
-
H. Kufluoglu, "MOSFET degradation due to negative bias temperature instability (NBTI) and hot carrier injection (HCI), and its implications for reliability-aware VLSI design," Ph.D. dissertation, Purdue Univ., West Lafayette, IN, 2007.
-
(2007)
MOSFET Degradation due to Negative bias Temperature Instability (NBTI) and hot Carrier Injection (HCI), and its Implications for Reliability-Aware VLSI Design
-
-
Kufluoglu, H.1
-
130
-
-
74049110866
-
Impact of transistor level degradation on product reliability
-
T. Nigam, "Impact of transistor level degradation on product reliability," in Proc. IEEE Custom Integr. Circuits Conf., 2009, pp. 431-438.
-
(2009)
Proc. IEEE Custom Integr. Circuits Conf.
, pp. 431-438
-
-
Nigam, T.1
-
131
-
-
0014630193
-
Electromigration failure modes in aluminum metallization for semiconductor devices
-
Sep.
-
J. R. Black, "Electromigration failure modes in aluminum metallization for semiconductor devices," Proc. IEEE, vol. 57, pp. 1587-1594, Sep. 1969.
-
(1969)
Proc. IEEE
, vol.57
, pp. 1587-1594
-
-
Black, J.R.1
-
132
-
-
0015142451
-
Electromigration and failure in electronics: An introduction
-
Oct.
-
F. M. d'Heurle, "Electromigration and failure in electronics: An introduction," Proc. IEEE, vol. 59, no. 10, pp. 1409-1418, Oct. 1971.
-
(1971)
Proc. IEEE
, vol.59
, Issue.10
, pp. 1409-1418
-
-
D'Heurle, F.M.1
-
133
-
-
0027187019
-
AC electromigration characterization and modeling of multilayered interconnects
-
L. M. Ting, J. S. May, W. R. Hunter, and J. W. McPherson, "AC electromigration characterization and modeling of multilayered interconnects," in Proc. IEEE Int. Rel. Phys. Symp., 1993, pp. 311-316.
-
(1993)
Proc. IEEE Int. Rel. Phys. Symp.
, pp. 311-316
-
-
Ting, L.M.1
May, J.S.2
Hunter, W.R.3
McPherson, J.W.4
-
134
-
-
70349670752
-
Thermomechanical reliability of 3-D ICs containing through silicon vias
-
K. H. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang, and P. S. Ho, "Thermomechanical reliability of 3-D ICs containing through silicon vias," in Proc. Electron. Compon. and Technol. Conf., 2009.
-
(2009)
Proc. Electron. Compon. and Technol. Conf.
-
-
Lu, K.H.1
Zhang, X.2
Ryu, S.-K.3
Im, J.4
Huang, R.5
Ho, P.S.6
-
135
-
-
77956216567
-
TSV stress aware timing analysis with applications to 3D-IC layout optimization
-
J.-S. Yang, K. Athikulwongse, Y.-J. Lee, S. K. Lim, and D. Z. Pan, "TSV stress aware timing analysis with applications to 3D-IC layout optimization," in Proc. ACM/IEEE Design Autom. Conf., 2010, pp. 803-806.
-
(2010)
Proc. ACM/ IEEE Design Autom. Conf.
, pp. 803-806
-
-
Yang, J.-S.1
Athikulwongse, K.2
Lee, Y.-J.3
Lim, S.K.4
Pan, D.Z.5
-
136
-
-
78650859591
-
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study
-
K. Athikulwongse, A. Chakraborty, J.-S. Yang, D. Z. Pan, and S. K. Lim, "Stress-driven 3D-IC placement with TSV keep-out zone and regularity study," in Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design, 2010, pp. 669-674.
-
(2010)
Proc. IEEE/ACM Int. Conf. on Comput.-Aided Design
, pp. 669-674
-
-
Athikulwongse, K.1
Chakraborty, A.2
Yang, J.-S.3
Pan, D.Z.4
Lim, S.K.5
|