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Volumn , Issue , 2006, Pages 217-224

A linear-time approach for static timing analysis covering all process corners

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; EIGENVALUES AND EIGENFUNCTIONS; ELECTRIC CURRENTS; INDUSTRIAL ENGINEERING; LEAD; MANGANESE COMPOUNDS; NETWORKS (CIRCUITS); PARAMETER ESTIMATION; STATIC ANALYSIS; STORM SEWERS; SYNTHETIC APERTURES; SYSTEMS ANALYSIS; TIME MEASUREMENT;

EID: 46149095291     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320139     Document Type: Conference Paper
Times cited : (8)

References (10)
  • 1
    • 0041633857 scopus 로고    scopus 로고
    • Computation and refinement of statistical bounds on circuit delay
    • June 2-6
    • A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula. Computation and refinement of statistical bounds on circuit delay. In Design Automation Conference, pages 348-353, June 2-6 2003.
    • (2003) Design Automation Conference , pp. 348-353
    • Agarwal, A.1    Blaauw, D.2    Zolotov, V.3    Vrudhula, S.4
  • 2
    • 4444343172 scopus 로고    scopus 로고
    • Variational delay metrics for interconnect timing analysis
    • June 7-11
    • K. Agarwal, D. Sylvester, D. Blaauw, F. Liu, S. Nassif, and S. Vrudhula. Variational delay metrics for interconnect timing analysis. In DAC, pages 381-384, June 7-11 2004.
    • (2004) DAC , pp. 381-384
    • Agarwal, K.1    Sylvester, D.2    Blaauw, D.3    Liu, F.4    Nassif, S.5    Vrudhula, S.6
  • 3
  • 4
    • 0346778721 scopus 로고    scopus 로고
    • Statistical timing alaysis considering spatial correlations using a single PERT-line traversal
    • November 9-13
    • H. Chang and S. Sapatnekar. Statistical timing alaysis considering spatial correlations using a single PERT-line traversal. In IEEE/ACM Int. Conf. on Computer-Aided Design (ICGAD), pages 621-625, November 9-13 2003.
    • (2003) IEEE/ACM Int. Conf. on Computer-Aided Design (ICGAD) , pp. 621-625
    • Chang, H.1    Sapatnekar, S.2
  • 8
    • 0028756124 scopus 로고
    • Modeling the "effective capacitance" for the rc interconnect of cmos gates
    • J. Quain, S. Pullela, and L. Pillage. Modeling the "effective capacitance" for the rc interconnect of cmos gates. IEEE Trans. on Computer-Aided Design, 13(12):1526-1535, 1994.
    • (1994) IEEE Trans. on Computer-Aided Design , vol.13 , Issue.12 , pp. 1526-1535
    • Quain, J.1    Pullela, S.2    Pillage, L.3
  • 9
    • 20344385187 scopus 로고    scopus 로고
    • Kluwer Academic Publishers, Norwell, MA, 1st edition
    • S. Sapatnekar. Timing. Kluwer Academic Publishers, Norwell, MA, 1st edition, 2004.
    • (2004) Timing
    • Sapatnekar, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.