Hierarchical analysis of power distribution networks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 2, 2002, Pages 159-168

  Zhao, Min ^a   Panda, Rajendran V ^a   Sapatnekar, Sachin S ^b   Blaauw, David ^c  

^a MOTOROLA INC   (United States)

^b University of Minnesota   (United States)

^c UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Circuit simulation; IR drop; Matrix sparsification; Partitioning; Power distribution networks; Power grid; Signal integrity

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; HIERARCHICAL SYSTEMS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; MATHEMATICAL MODELS; VLSI CIRCUITS;

CIRCUIT SIMULATION; MATRIX SPARSIFICATION; POWER DISTRIBUTION NETWORKS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036474411     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.980256     Document Type: Article

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