A yield model for integrated circuits and its application to statistical timing analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 3, 2007, Pages 574-591

  Najm, Farid N ^a,b   Menezes, Noel ^a,c   Ferzli, Imad A ^a,b  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

^c INTEL CORPORATION   (United States)

Author keywords

Correlations; Die to die variations; Generic critical path; Parametric yield; Principal component analysis; Statistical timing analysis; Timing margin; Virtual corner; Within die variations

Indexed keywords

STATISTICAL TIMING ANALYSIS; TIMING MARGIN; VIRTUAL CORNER; WITHIN-DIE VARIATIONS;

CORRELATION METHODS; DATA PROCESSING; MATHEMATICAL MODELS; PRINCIPAL COMPONENT ANALYSIS; SCHEDULING; STATISTICAL METHODS;

INTEGRATED CIRCUITS;

EID: 33847759065     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.883924     Document Type: Conference Paper

References (32)

1. S. W. Director, W. Maly, and A. J. Strojwas, VLSI Design Manufacturing for Yield Enhancement. Boston, MA: Kluwer, 1990.
2. W. Moore, W. Maly, and A. Strojwas, Eds., Yield Modelling and Defect Tolerance in VLSI, Bristol, U.K.: Adam Hilger, 1987.
3. K. Bernstein, K. M. Carrig, C. M. Durham, P. R. Hansen, D. Hogenmiller, E. J. Nowak, and N. J. Rohrer, High Speed CMOS Design Styles. Boston, MA: Kluwer, 1999.
4. J. B. Khare and W. Maly, From Contamination to Defects, Faults, and Yield Loss. Boston, MA: Kluwer, 1996.
5. M. Eisele, J. Berthold, D. Schmitt-Landsiedel, and R. Mahnkopf, "The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 5, no. 4, pp. 360-368, Dec. 1997.
6. A. Gattiker, S. Nassif, R. Dinakar, and C. Long, "Timing yield estimation from static timing analysis," in Proc. IEEE Int. Symp. Quality Electron. Des., San Jose, CA, Mar. 26-28, 2001, pp. 437-442.
7. S. R. Nassif, Statistical Worst-Case Analysis for Integrated Circuits Statistical Approach to VLSI, ser. Advances in CAD for VLSI, vol. 8, S. W. Director and W. Maly, Eds. Amsterdam, The Netherlands: North-Holland, 1994.
8. K. Singhal and V. Visvanathan, "Statistical device models for worst case files and electrical test data," IEEE Trans. Semicond. Manuf., vol. 12, no. 4, pp. 470-484, Nov. 1999.
9. D. Boning and S. Nassif, "Models of process variations in device and interconnect," in Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. J. Bowhill, and F. Fox, Eds. New York: IEEE Press, 2001, ch. 6.
10. L. Mizrukhin, J. Huey, and S. Mehta, "Prediction of product yield distributions from wafer parametric measurements of CMOS circuits," IEEE Trans. Semicond. Manuf., vol. 5, no. 2, pp. 88-93, May 1992.
11. K. K. Low and S. W. Director, "A new methodology for the design centering of IC fabrication processes," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 10, no. 7, pp. 895-903, Jul. 1991.
12. R. W. Dutton and A. J. Strojwas, "Perspectives on technology and technology-driven CAD," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 12, pp. 1544-1560, Dec. 2000.
13. S. R. Nassif, "Within-chip variability analysis," in Proc. IEEE Int. Electron. Devices Meeting, San Francisco, CA, Dec. 6-9, 1998, pp. 283-286.
14. B. E. Stine, D. S. Boning, and J. E. Chung, "Analysis and decomposition of spatial variation in integrated circuit processes and devices," IEEE Trans. Semicond. Manuf., vol. 10, no. 1, pp. 24-41, Feb. 1997.
15. V. Mehrotra, S. L. Sam, D. Boning, A. Chandrakasan, R. Vallishayee, and S. Nassif, "A methodology for modeling the effects of systematic within-die interconnect and device variations on circuit performance," in Proc. ACM/IEEE Des. Autom. Conf., Los Angeles, CA, Jun. 5-9, 2000, pp. 172-175.
16. J. A. G. Jess, K. Kalafala, W. R. Naidu, R. H. J. M. Otten, and C. Visweswariah, "Statistical timing for parametric yield prediction of digital integrated circuits," in Proc. ACM/IEEE Des. Autom. Conf., Anaheim, CA, Jun. 2-6, 2003, pp. 932-937.
17. C. Visweswariah, "Death, taxes and failing chips," in Proc. ACM/IEEE Den. Autom. Conf., Anaheim, CA, Jun. 2-6, 2003, pp. 343-347.
18. A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Computation and refinement of statistical bounds on circuit delay," in Proc. ACM/IEEE Des. Autom. Conf., Anaheim, CA, Jun. 2-6, 2003, pp. 348-353.
19. A. Agarwal, D. Blaauw, and V. Zolotov, "Statistical timing analysis for intra-die process variations with spatial correlations," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., San Jose, CA, Nov. 9-13, 2003, pp. 900-907.
20. H. Chang and S. S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single PERT-like traversal," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., San Jose, CA, Nov. 9-13, 2003, pp. 621-625.
21. A. Devgan and C. Kashyap, "Block-based static timing analysis with uncertainty," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., San Jose, CA, Nov. 9-13, 2003, pp. 607-614.
22. S. Bhardwaj, S. B. Vrudhula, and D. Blaauw, "Tau: Timing analysis under uncertainty," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., San Jose, CA, Nov. 9-13, 2003, pp. 615-620.
23. K. A. Bowman and J. D. Meindl, "Impact of within-die parameter fluctuations on future maximum clock frequency distributions," in Proc. IEEE Custom Integr. Circuits Conf., San Diego, CA, May 6-9, 2001, pp. 229-232.
24. F. N. Najm and N. Menezes, "Statistical timing analysis based on a timing yield model," in Proc. ACM/IEEE Des. Autom. Conf., San Diego, CA, Jun. 7-11, 2004, pp. 460-465.
25. X. Bai, C. Visweswariah, P. N. Strenski, and D. J. Hathaway, "Uncertainty-aware circuit optimization," in Proc. Des. Autom. Conf., New Orleans, LA, Jun. 10-14, 2002, pp. 58-63.
26. M. S. Srivastava, Methods of Multivariate Statistics. New York: Wiley-Interscience, 2002.
27. J. M. Rabaey, Digital Integrated Circuits: A Design Perspective. Upper Saddle River, NJ: Prentice-Hall, 1996.
28. Y. Liu, L. T. Pileggi, and A. J. Strojwas, "Model order-reduction of RC(L) interconnect including variational analysis," in Proc. Des. Autom. Conf., New Orleans, LA, Jun. 21-25, 1999, pp. 201-206.
29. E. Acar, S. Nassif, Y. Liu, and L. T. Pileggi, "Time-domain simulation of variational interconnect models," in Proc. IEEE Int. Symp. Quality Electron. Des., San Jose, CA, Mar. 18-21, 2002, pp. 419-424.
30. E. Malavasi, S. Zanella, M. Cao, J. Uschersohn, M. Misheloff, and C. Guardiani, "Impact analysis of process variability on clock skew," in Proc. IEEE Int. Symp. Quality Electron. Des., San Jose, CA, Mar. 18-21, 2002, pp. 129-132.
31. A. Papoulis, Probability, Random Variables, and Stochastic Processes. New York: McGraw-Hill, 1984.
32. S. Boyd and L. Vandenberghe, Convex Optimization. New York: Cambridge Univ. Press, 2004. [Online]. Available: http://www.stanford.edu/~boyd/ cvxbook.html