-
1
-
-
0033719421
-
Wattch: A framework for architectural-level power analysis and optimizations
-
Vancouver, British Columbia, June
-
D. Brooks, V. Tiwari, and M Martonosi, "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations," In Proceedings of the 27th International Symposium on Computer Architecture (ISCA), Vancouver, British Columbia, June 2000.
-
(2000)
Proceedings of the 27th International Symposium on Computer Architecture (ISCA)
-
-
Brooks, D.1
Tiwari, V.2
Martonosi, M.3
-
4
-
-
0033701594
-
B*-trees: A new representation for non-slicing floorplans
-
June
-
Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu, "B*-trees: A New Representation for Non-Slicing Floorplans," In Proceedings of the 37th Conference on Design Automation (DAC), pp. 458-463, June 2000.
-
(2000)
Proceedings of the 37th Conference on Design Automation (DAC)
, pp. 458-463
-
-
Chang, Y.-C.1
Chang, Y.-W.2
Wu, G.-M.3
Wu, S.-W.4
-
6
-
-
0043092230
-
Microarchitecture evaluation with physical planning
-
June
-
J. Cong, A. Jagannathan, G. Reinman, and M. Romesis, " Microarchitecture Evaluation with Physical Planning," In Proceedings of the 36th Conference on Design Automation (DAC), pp. 32-35, June 2003.
-
(2003)
Proceedings of the 36th Conference on Design Automation (DAC)
, pp. 32-35
-
-
Cong, J.1
Jagannathan, A.2
Reinman, G.3
Romesis, M.4
-
7
-
-
4444333238
-
Profile-guided microarchitectural floorplanning for deep submicron processor design
-
June
-
M. Ekpanyapong, J. R. Minz, T. Watewai, H.-H. S. Lee, and S. K. Lim, "Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design," In Proceedings of the 36th Conference on Design Automation (DAC), pp. 634-639, June, 2004.
-
(2004)
Proceedings of the 36th Conference on Design Automation (DAC)
, pp. 634-639
-
-
Ekpanyapong, M.1
Minz, J.R.2
Watewai, T.3
Lee, H.-H.S.4
Lim, S.K.5
-
8
-
-
0003815341
-
Managing the impact of increasing microprocessor power consumption
-
S. Gunther, F. Binns, D. M. Canmean, and J. C. Hall, "Managing the Impact of Increasing Microprocessor Power Consumption," Intel Technology Journal, Q1 2001.
-
(2001)
Intel Technology Journal
, vol.Q1
-
-
Gunther, S.1
Binns, F.2
Canmean, D.M.3
Hall, J.C.4
-
10
-
-
4444374512
-
Compact thermal modeling for temperature-aware design
-
June
-
W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy, "Compact Thermal Modeling for Temperature-Aware Design," In Proceedings of the 36th Conference on Design Automation (DAC), pp. June 2004.
-
(2004)
Proceedings of the 36th Conference on Design Automation (DAC)
-
-
Huang, W.1
Stan, M.R.2
Skadron, K.3
Sankaranarayanan, K.4
Ghosh, S.5
Velusamy, S.6
-
11
-
-
26444479778
-
Optimization by simulated annealing
-
May
-
S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by Simulated Annealing," Science, vol. 220, no. 4598, pp.671-680, May, 1983.
-
(1983)
Science
, vol.220
, Issue.4598
, pp. 671-680
-
-
Kirkpatrick, S.1
Gelatt, C.D.2
Vecchi, M.P.3
-
13
-
-
0006704808
-
Technology independent area and delay estimates for microprocessor building blocks
-
Department of Computer Sciences, the University of Texas at Austin
-
S. Gupta, S. W. Keckler, and D. Burger, "Technology Independent Area and Delay Estimates for Microprocessor Building Blocks," Technical Report 2000-05, Department of Computer Sciences, The University of Texas at Austin, 2000.
-
(2000)
Technical Report
, vol.2000
, Issue.5
-
-
Gupta, S.1
Keckler, S.W.2
Burger, D.3
-
14
-
-
28444464379
-
Joint exploration of architectural and physical design spaces with thermal consideration
-
National Taiwan University
-
Y. W. Wu, C. L. Yang, P. H. Yuh, and Y. W. Chang, "Joint Exploration of Architectural and Physical Design Spaces with Thermal Consideration," Technical Report 05-04, National Taiwan University, 2005.
-
(2005)
Technical Report
, vol.5
, Issue.4
-
-
Wu, Y.W.1
Yang, C.L.2
Yuh, P.H.3
Chang, Y.W.4
|