Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 86-89

  Goplen, Brent ^a   Sapatnekar, Sachin ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

RUN TIME EFFICIENCY; THERMAL PLACEMENT;

ALGORITHMS; BOUNDARY CONDITIONS; COMPUTER SIMULATION; CONSTRAINT THEORY; FINITE DIFFERENCE METHOD; FINITE ELEMENT METHOD; HEAT CONDUCTION; HEAT PROBLEMS; HEAT SINKS; HIGH TEMPERATURE EFFECTS; ISOTHERMS; ITERATIVE METHODS; LINEAR EQUATIONS; MICROPROCESSOR CHIPS; SIMULATED ANNEALING; THERMAL CONDUCTIVITY;

INTEGRATED CIRCUITS;

EID: 0347409236     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, "3-D ICs: A Novel Chip Design for Improving Deep Submicrometer Interconnect Performance and Systems-on-Chip Integration," in Proc. of the IEEE, vol. 89, no. 5, pp. 602-633, May 2001.
2. M. Chan and P. K. Ko, "Development of a Viable 3D Integrated Circuit Technology," Science in China, vol. 44, no. 4, pp. 241-248, August 2001.
3. G. Chen and S. S. Sapatnekar, "Partition-Driven Standard Cell Thermal Placement," in Proc. of the ACM Int. Symp. on Physical Design, pp. 75-80, 2003.
4. C. N. Chu and D. F. Wong, "A Matrix Synthesis Approach to Thermal Placement," in Proc. Int. Symp. on Physical Design, pp. 163-168, 1997.
5. H. Eisenmann and F. M. Johannes, "Generic Global Placement and Floorplanning," in Proc. Design Automation Conf., pp. 269-274, June 1998.
6. D. L. Logan, A First Course in the Finite Element Method, 3rd ed., Brooks/Cole Pub. Co., 2002.
7. F. Mo, A. Tabbara, and R. K. Brayton, "A Force-Directed Macro-Cell Placer," in Proc. of the Int. Conf. on Comput. Aided Des., pp. 177-181, Nov. 2000.
8. M. Reber and R. Tielert, "Benefits of Vertically Stacked Integrated Circuits for Sequential Logic," in Proc. IEEE Int. Symp. on Circuits and Syst., vol. 4, pp. 121-124, May 1996.
9. T. Tanprasert, "An Analytical 3-D Placement that Reserves Routing Space," in Proc. IEEE Int. Symp. on Circuits and Syst., vol. 3, pp. 69 -72, 2000.
10. C. H. Tsai and S. M. Kang, "Cell-Level Placement for Improving Substrate Thermal Distribution," IEEE Trans. on Comput.-Aided Des., vol. 19, no. 2, pp. 253-266, Feb. 2000.
11. http://er.cs.ucla.edu/benchmarks/ibm-place/
12. www.cbl.ncsu.edu/pub/Benchmark_dirs/LayoutSynth92
13. www.tu-dresden.de/mwism/skalicky/laspack/laspack.html