메뉴 건너뛰기




Volumn , Issue , 2005, Pages 321-324

Circuit optimization using statistical static timing analysis

Author keywords

Algorithms; Optimization; Performance; Reliability

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; HEURISTIC METHODS; OPTIMIZATION; RELIABILITY; STATISTICAL METHODS;

EID: 27944476890     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193825     Document Type: Conference Paper
Times cited : (69)

References (12)
  • 1
    • 0034429814 scopus 로고    scopus 로고
    • Delay variability: Sources, impacts and trends
    • S. Nassif, "Delay Variability: Sources, Impacts and Trends," Proceedings of ISSCC, 2000.
    • (2000) Proceedings of ISSCC
    • Nassif, S.1
  • 3
    • 0348040110 scopus 로고    scopus 로고
    • Block-based static timing analysis with uncertainty
    • A. Devgan, C. Kashyap, "Block-based Static Timing Analysis with Uncertainty," ICCAD 2003, pp.607-614.
    • ICCAD 2003 , pp. 607-614
    • Devgan, A.1    Kashyap, C.2
  • 4
    • 0346778721 scopus 로고    scopus 로고
    • Statistical timing analysis considering spatial correlations using a single pert-like traversal
    • H. Chang, S. Sapatnekar, "Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-like Traversal," ICCAD'03.
    • ICCAD'03
    • Chang, H.1    Sapatnekar, S.2
  • 5
    • 0034997869 scopus 로고    scopus 로고
    • Increase in delay uncertainty by performance optimization
    • H. Hashimoto, H. Onodera. "Increase in delay uncertainty by performance optimization", ISCAS 2001, pp. 379-382.
    • ISCAS 2001 , pp. 379-382
    • Hashimoto, H.1    Onodera, H.2
  • 7
  • 8
    • 4444333242 scopus 로고    scopus 로고
    • A methodology to improve timing yield in the presence of process variations
    • S. Raj, S. Vrudhula, J. Wang. "A methodology to improve timing yield in the presence of process variations", DAC 2004.
    • DAC 2004
    • Raj, S.1    Vrudhula, S.2    Wang, J.3
  • 9
    • 33646928098 scopus 로고    scopus 로고
    • Statistical timing based optimization using gate sizing
    • A. Agarwal, K. Chopra, D. Blaauw, "Statistical Timing Based Optimization using Gate Sizing", DATE 2005.
    • DATE 2005
    • Agarwal, A.1    Chopra, K.2    Blaauw, D.3
  • 10
    • 0036474722 scopus 로고    scopus 로고
    • Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
    • Feb
    • K. Bowman et. al., "Impact of die-to-die and within-die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration," IEEE J. Solid-State Circuit, Feb 2002.
    • (2002) IEEE J. Solid-state Circuit
    • Bowman, K.1
  • 11
    • 27944507991 scopus 로고    scopus 로고
    • Personal communication, IBM Corp, Burlington, VT
    • Personal communication, Kerry Bernstein, IBM Corp, Burlington, VT.
    • Bernstein, K.1
  • 12
    • 0002609165 scopus 로고
    • A neutral netlist of 10 combinatorial benchmark circuits
    • F. Brglez, H.Fujiwara, "A Neutral Netlist of 10 Combinatorial Benchmark Circuits", Proc. ISCAS, 1985, pp.695-698.
    • (1985) Proc. ISCAS , pp. 695-698
    • Brglez, F.1    Fujiwara, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.