Placement of 3D ICs with thermal and interlayer via considerations

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 626-631

  Goplen, Brent ^a   Sapatnekar, Sachin ^b  

^a IBM   (United States)

^b UNIVERSITY OF MINNESOTA   (United States)

Author keywords

3 D IC; 3 D VLSI; Interlayer vias; Placement; Temperature; Thermal optimization

Indexed keywords

INTERLAYER VIAS; THERMAL OPTIMIZATION; WIRELENGTHS;

CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT; THERMAL EFFECTS; THREE DIMENSIONAL;

VLSI CIRCUITS;

EID: 34547301387     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375239     Document Type: Conference Paper

References (19)

1. T. Tanprasert, "An Analytical 3-D Placement that Reserves Routing Space," ISCAS '00, 69-72.
2. B. Goplen and S. S. Sapatnekar, "Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach," ICCAD '03, 86-89.
3. I. Kaya, M. Olbrich, and E. Barke, "3-D Placement Considering Vertical Interconnects," Proc. IEEE Int. SOC Conf. '03, 257- 258.
4. R. Hentschke, G. Flach, F. Pinto, and R. Reis, "Quadratic Placement for 3D Circuits Using Z-Cell Shifting, 3D Iterative Refinement and Simulated Annealing," Proc. Symp. on Integrated Circuits and Syst. Des. '06, 220-225.
5. Y. Deng and W. Maly, "Interconnect Characteristics of 2.5-D System Integration Scheme," ISPD '01, 171-175.
6. S. Das, A. Chandrakasan, and R. Reif, "Design Tools for 3-D Integrated Circuits," ASP-DAC '03, 53-56.
7. C. N. Chu and D. F. Wong, "A Matrix Synthesis Approach to Thermal Placement,"ISPD '97, 163-168.
8. B. Obermeier and F. M. Johannes, "Temperature-Aware Global Placement," ASP-DAC '04, 143-148.
9. C. H. Tsai and S. M. Kang, "Cell-Level Placement for Improving Substrate Thermal Distribution," TCAD, 2000, 19(2), 253-266.
10. G. Chen and S. S. Sapatnekar, "Partition-Driven Standard Cell Thermal Placement,"ISPD '03, pp. 75-80.
11. A. E. Dunlop and B. W. Kemighan, "A Procedure for Placement of Standard Cell VLSI Circuits," TCAD, 1985, 4(1), 92-98.
12. C.-C. Chang, J. Cong, M. Romesis, and M. Xie, "Optimality and Scalability Study of Existing Placement Algorithms," TCAD, 2004, 23(4), 537-549.
13. N. Viswanathan and C. Chu, "FastPlace: Efficient Analytical Placement using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model," ISPD '04, 26-33.
14. M. Pan, N. Viswanathan, and C. Chu, "An Efficient and Effective Detailed Placement Algorithm," ICCAD '05, 48-55.
15. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multilevel Hypergraph Partitioning: Applications in VLSI Domain," IEEE Trans. on VLSI Syst., 1999, 7(1), 69-79.
16. http://er.cs.ucla.edu/benchmarks/ibm-place/
17. J. Bums, L. McIlrath, C. Keast, C. Lewis, A. Loomis, K. Warner, and P. Wyatt, "Three-Dimensional Integrated Circuits for Low-Power, High-Bandwidth Systems on a Chip," ISSCC Digest of Technical Papers, 2001, 268-269.
18. K. Warner, J. Burns, C. Keast, R. Kunz, D. Lennon, A. Loomis, W. Mowers, and D. Yost, "Low-Temperature Oxide-Bonded Three-Dimensional Integrated Circuits," IEEE International SOI Conference Proceedings, 2002, 123-124.
19. J. Cong, "Challenges and Opportunities for Design Innovations in Nanometer Technologies," Invited SRC Design Sciences Concept Paper, 1998, 1-15.