Congestion-driven codesign of power and signal networks

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 64-69

  Su, Haihua ^a   Hu, Jiang ^a   Sapatnekar, Sachin S ^b   Nassif, Sani R ^a  

^a IBM   (United States)

^b UNIVERSITY OF MINNESOTA   (United States)

Author keywords

Codesign; Power grid noise; Signal routing; Wire congestion

Indexed keywords

SIGNAL ROUTING;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; CONGESTION CONTROL (COMMUNICATION); ITERATIVE METHODS; SIGNAL PROCESSING; SPURIOUS SIGNAL NOISE; WIRE;

NANOTECHNOLOGY;

EID: 0036058076     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2002.1012595     Document Type: Article

References (22)

1. A practical methodology for early buffer and wire resource allocation
2. Prim-Dijkstra tradeoffs for improved performance-driven routing tree design
3. Power supply noise analysis methodology for deep-submicron VLSI chip design
4. Interconnect and circuit modeling techniques for full-chip power supply noise analysis
5. Global routing based on steiner min-max tree
6. Noise considerations in circuit optimization
7. The generalized adjoint network and network sensitivities
8. Sensitivity computation in piecewise approximation circuit simulation
9. A timing-constrained algorithm for simultaneous routing of multiple nets
10. Simultaneous signal and power routing under Kerf model
11. A simple yet effective technique for global wiring
12. Fast power grid simulation
13. A global router based on a multicommodity flow model
14. Fast analysis and optimization of power/ground networks
15. An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
16. Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings
17. Routing and techniques for gate array
18. Area minimization of power distribution network using efficient nonlinear programming techniques
19. Hierarchical analysis of power distribution networks