Statistical timing analysis considering spatial correlations using a single PERT-like traversal

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 621-625

  Chang, Hongliang ^a   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CUMULATIVE DENSITY FUNCTIONS (CDF); STATIC TIMING ANALYSIS (STA);

ALGORITHMS; COMPUTATIONAL METHODS; COMPUTER CIRCUITS; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; MONTE CARLO METHODS; OPTICAL INTERCONNECTS; PROBABILITY DENSITY FUNCTION; PROBABILITY DISTRIBUTIONS; PROCESS CONTROL; STATISTICAL METHODS;

DELAY CIRCUITS;

EID: 0346778721     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. M. Berkelaar, "Statistical Delay Calculation, a Linear Time Method," in Proc. TAU, pp. 15-24, 1997.
2. A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Statistical Timing Analysis Using Bounds and Selective Enumeration," In Proc. TAU, pp. 29-36, 2002.
3. J. J. Liou, K. T. Cheng, S. Kundu, and A. Krstic, "Fast Statistical Timing Analysis By Probabilistic Event Propagation," in Proc. DAC, pp. 661-666, 2001.
4. S. Naidu, "Timing Yield Calculation Using an Impulse-Train Approach," in Proc. Int. Conf. on VLSI Design, Bangalore, pp. 219-224, 2002.
5. S. Tsukiyama, M. Tanaka, and M. Fukui, "A New Statistical Static Timing Analyzer Considering Correlation Between Delays," in Proc. TAU, pp. 27-33, Dec 2000.
6. J. J. Liou, A. Krstic, L. C. Wang, and K. T. Cheng, "False-Path-Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation," in Proc. ICCAD, pp. 566-569, 2002.
7. M. Orshansky and K. Keutzer, "A General Probabilistic Framework for Worst Case Timing Analysis," In Proc. DAC, pp. 556-561, 2002.
8. B. Choi and D. M. H. Walker, "Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation," in Proc. VLSI Test Symp., pp. 49-54, 2000.
9. A. Agarwal, D. Blaauw, S. Sundareswaran, V. Zolotov, M. Zhou, K. Gala, and K. Panda,"Path-Based Statistical Timing Analysis Considering Inter- and Intra-die Correlations," in Proc. TAU, pp. 16-21, 2002.
10. Y. Liu, S. R. Nassif, L. T. Pileggi, and A. J. Strojwas, "Impact of Interconnect Variations on the Clock Skew of a Gigahertz Microprocessor," In Proc. DAC, pp. 168-171, 2000.
11. D. F. Morrison, "Multivariate Statistical Methods," New York: McGraw-Hill, 1976.
12. C. E. Clark, "The Greatest of a Finite Set of Random Variables," Operations Research, vol. 9, pp. 85-91, 1961.
13. J. Cong, "Challenges and Opportunities for Design Innovations in Nanometer Technologies," SRC Design Science Concept Paper, 1997.
14. S. Nassif, "Delay Variability: Sources, Impact and Trends," in Proc. ISSCC, pp. 368-369, 2000
15. A. Caldwell, A. B. Kahng, and I. Markov, "Capo: a large-scale fixed-die placer," avail. at http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/Placement.