Accelerated chip-level thermal analysis using multilayer Green's function

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 2, 2007, Pages 325-343

  Wang, Baohua ^a,b   Mazumder, Pinaki ^b  

^a IEEE   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Algorithms; Discrete cosine transforms; Distributed parameter circuits; Electrothermal effects; Green's function; Temperature

Indexed keywords

DISCRETE COSINE TRANSFORMS; DISTRIBUTED PARAMETER CIRCUITS; ELECTROTHERMAL EFFECTS; MULTILAYER CHIP STRUCTURE;

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; GREEN'S FUNCTION; HEAT CONDUCTION; THERMOANALYSIS; TRANSISTORS;

ULSI CIRCUITS;

EID: 33846609148     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.883919     Document Type: Conference Paper

References (45)

1. T. Sakurai and A. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584-594, Apr. 1990.
2. K. Kanda, K. Nose, H. Kawaguchi, and T. Sakurai, "Design impact of positive temperature dependence on drain currentin sub-1-V CMOS VLSIs," IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1559-1564, Oct. 2001.
3. C.-I. Kim, H. Soeleman, and K. Roy, "Ultra-low-power DLMS adaptive filter for hearing aid applications," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 6, pp. 1058-1067, Dec. 2003.
4. B. Calhoun, A. Wang, and A. Chandrakasan, "Modeling and sizing for minimum energy operation in subthreshold circuits," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1778-1786, Sep. 2005.
5. K. Banerjee, A. Amerasekera, G. Dixit, and C. Hu, "The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal," in IEDM Tech. Dig., Dec. 1996, pp. 65-68.
6. D. Chen, E. Li, E. Rosenbaum, and S.-M. Kang, "Interconnect thermal modeling for accurate simulation of circuit timing and reliability," IEEE Trans. Comput.-Aided Design Integr. Ciruits Syst., vol. 19, no. 2, pp. 197-205, Feb. 2000.
7. M. R. Casu, M. Graziano, G. Masera, G. Piccinini, M. M. Prono, and M. Zamboni, "Clock distribution network optimization under self-heating and timing constraints," in Proc. PATMOS, Sep. 2002, pp. 198-208.
8. K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu, "On thermal effects in deep sub-micron VLSI interconnects," in Proc. ACM/IEEE Des. Autom. Conf., Jun. 1999, pp. 885-891.
9. M. Casu, M. Graziano, G. Masera, G. Piccinini, and M. Zamboni, "An electromigration and thermal model of power wires for a priori high-level reliability prediction," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 4, pp. 349-358, Apr. 2004.
10. W. Huang, M. Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy, "Compact thermal modeling for temperature-aware design," in Proc. ACM/IEEE Des. Autom. Conf., Jun. 2004, pp. 878-883.
11. L. Codecasa, D. D'Amore, and P. Maffezzoni, "An Arnoldi based thermal network reduction method for electro-thermal analysis," IEEE Trans. Compon. Packag. Technol., vol. 26, no. 1, pp. 186-192, Mar. 2003.
12. T.-Y. Wang and C. Chen, "3-D thermal-ADI: A linear-time chip level transient thermal simulator," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, no. 12, pp. 1434-1445, Dec. 2002.
13. A. Odabasioglu, M. Celik, and L. Pileggi, "PRIMA: Passive reduced-order interconnect macromodeling algorithm," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 17, no. 8, pp. 645-654, Aug. 1998.
14. Y.-K. Cheng and S.-M. Kang, "A temperature-aware simulation environment for reliable ULSI chip design," IEEE Trans. Comput.-Aided Design Integr. Ciruits Syst., vol. 19, no. 10, pp. 1211-1220, Oct. 2000.
15. B. Wang and P. Mazumder, "Fast thermal analysis for VLSI circuits via semi-analytical Green's function in multi-layer materials," in Proc. Int. Symp. Circuits and Syst., May 2004, vol. 2, pp. 409-412.
16. Y. Zhan and S. Sapatnekar, "Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up," in Proc. Asia and South Pacific Des. Autom. Conf., Jan. 2005, vol. 1, pp. 87-92.
17. J. V. Beck, K. Cole, and A. Haji-Sheikh, Heat Conduction Using Green's Functions. Bristol, PA: Hemisphere, 1992.
18. K. Banerjee, S. Souri, P. Kapur, and K. Saraswat, "3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proc. IEEE, vol. 89, no. 5, pp. 602-633, May 2001.
19. W. Batty, C. Christoffersen, A. Panks, S. David, C. Snowden, and M. Steer, "Electrothermal CAD of power devices and circuits with fully physical time-dependent compact thermal modeling of complex nonlinear 3-D systems," IEEE Trans. Compon. Packag. Technol., vol. 24, no. 4, pp. 566-590, Dec. 2001.
20. M. Rencz, V. Szekely, A. Poppe, and B. Courtois, "Inclusion of RC compact models of packages into board level thermal simulation tools," in Proc. 18th IEEE Semicond. Thermal Meas. and Manage. Symp., 2002, pp. 71-76.
21. K. Nabors and J. White, "FastCap: A multipole accelerated 3-D capacitance extraction program," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 10, no. 11, pp. 1447-1459, Nov. 1991.
22. T.-Y. Chou and Z. Cendes, "Capacitance calculation of IC packages using the finite element method and planes of symmetry," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 13, no. 9, pp. 1159-1166, Sep. 1994.
23. J. Phillips and J. White, "A precorrected-FFT method for electrostatic analysis of complicated 3-D structures," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 16, no. 10, pp. 1059-1072, Oct. 1997.
24. J. Zhao, W. Dai, S. Kadur, and D. Long, "Efficient three-dimensional extraction based on static and full-wave layered Green's functions," in Proc. ACM/IEEE Des. Autom. Conf., Jun. 1998, pp. 224-229.
25. A. Niknejad, R. Gharpurey, and R. Meyer, "Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 17, no. 4, pp. 305-315, Apr. 1998.
26. C. Xu, T. Fiez, and K. Mayaram, "On the numerical stability of Green's function for substrate coupling in integrated circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 4, pp. 653-658, Apr. 2005.
27. A. Kokkas, "Thermal analysis of multiple-layer structures," IEEE Trans. Electron Devices, vol. ED-21, no. 11, pp. 674-681, Nov. 1974.
28. J. Albers, "An exact recursion relation solution for the steady-state surface temperature of a general multilayer structure," IEEE Trans. Compon., Packag., Manuf. Technol. A, vol. 18, no. 1, pp. 31-38, Mar. 1995.
29. A. Csendes, V. Szekely, and M. Rencz, "An efficient thermal simulation tool for ICs, microsystem elements and MCMs: The μS-THERMANAL, " Microelectron. J., vol. 29, no. 4/5, pp. 241-255, 1998.
30. Y. C. Gerstenmaier and G. Wachutka, "Time dependent temperature fields calculated using eigenfunctions and eigenvalues of the heat conduction equation,"Microelectron. J., vol. 32, no. 10, pp. 801-808, Oct. 2001.
31. J.-M. Dorkel, P. Tounsi, and P. Leturcq, "Three-dimensional thermal modeling based on the two-port network theory for hybrid or monolithic integrated power circuits," IEEE Trans. Compon., Packag., Manuf. Technol. A, vol. 19, no. 4, pp. 501-507, Dec. 1996.
32. D. Maillet, S. Andre, J. C. Batsale, A. Degiovanni, and C. Moyne, Thermal Quadrupoles: Solving the Heat Equation Through Integral Transforms. Hoboken, NJ: Wiley, 2000.
33. Y. Gerstenmaier and G. Wachutka, "Transient temperature fields with general nonlinear boundary conditions in electronic systems," IEEE Trans. Compon. Packag. Technol., vol. 28, no. 1, pp. 23-33, Mar. 2005.
34. Y.-K. Cheng, P. Raha, C.-C. Teng, E. Rosenbaum, and S.-M. Kang, "ILLIADS-T: An electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 17, no. 8, pp. 668-681, Aug. 1998.
35. J. Clementi, J. McCreary, T. Niu, J. Palomaki, J. Varcoe, and G. Hill, "Flip-chip encapsulation on ceramic substrates," in Proc. Electron. Compon. and Technol. Conf., Jun. 1993, pp. 175-181.
36. J. Parry, H. Rosten, and G. Kromann, "The development of component-level thermal compact models of a C4/CBGA interconnect technology: The Motorola PowerPC 603 and PowerPC 604 rise microprocessors," IEEE Trans. Compon., Packag., Manuf. Technol. A, vol. 21, no. 1, pp. 104-112, Mar. 1998.
37. R. Crampagne, M. Ahmadpanah, and J.-L. Guiraud, "A simple method for determining the Green's function for a large class of MIC lines having multilayered dielectric structures," IEEE Trans. Microw. Theory Tech., vol. MTT-26, no. 2, pp. 82-87, Feb. 1978.
38. J. Brown and R. Churchill, Fourier Series and Boundary Value Problems, 5th ed. New York: McGraw-Hill, 1993.
39. R. H. Joseph, Microwave Theory and Techniques. Cambridge, MA: Boston Technical Publishers, 1965.
40. D. M. Pozar, Microwave Engineering. Reading, MA: Addison-Wesley, 1990.
41. V. Szekely, A. Poppe, M. Rencz, M. Rosental, and T. Teszeri, "THERMAN: A thermal simulation tool for IC chips, microstructures and PW boards," Microelectron. J., vol. 40, no. 3, pp. 517-524, Mar. 2000.
42. V. Szekely, "THERMODEL: A tool for compact dynamic thermal model generation," Microelectron. J., vol. 29, no. 4, pp. 257-267, Apr. 1998.
43. _, "Identification of RC networks by deconvolution: Chances and limits," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 45, no. 3, pp. 244-258, Mar. 1998.
44. N. Ahmed, T. Natarjan, and K. R. Rao, "Discrete cosine transform," IEEE Trans. Comput., vol. C-23, no. 1, pp. 90-93, Jan. 1974.
45. G. J. Miao and M. A. Clements, Digital Signal Processing and Statistical Classification. Norwood, MA: Artech, 2002.